go.mod: github.com/minio/sha256-simd v1.0.1
https://github.com/minio/sha256-simd/compare/v1.0.0...v1.0.1 Signed-off-by: Akihiro Suda <akihiro.suda.cz@hco.ntt.co.jp>
This commit is contained in:
Akihiro Suda
parent
1f2216cc78
commit
68abb525a5
4
go.mod
4
go.mod
@ -37,7 +37,7 @@ require (
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github.com/hashicorp/go-multierror v1.1.1
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github.com/hashicorp/go-multierror v1.1.1
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github.com/intel/goresctrl v0.3.0
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github.com/intel/goresctrl v0.3.0
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github.com/klauspost/compress v1.16.7
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github.com/klauspost/compress v1.16.7
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github.com/minio/sha256-simd v1.0.0
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github.com/minio/sha256-simd v1.0.1
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github.com/moby/locker v1.0.1
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github.com/moby/locker v1.0.1
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github.com/moby/sys/mountinfo v0.6.2
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github.com/moby/sys/mountinfo v0.6.2
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github.com/moby/sys/sequential v0.5.0
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github.com/moby/sys/sequential v0.5.0
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@ -102,7 +102,7 @@ require (
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github.com/grpc-ecosystem/grpc-gateway/v2 v2.7.0 // indirect
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github.com/grpc-ecosystem/grpc-gateway/v2 v2.7.0 // indirect
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github.com/hashicorp/errwrap v1.1.0 // indirect
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github.com/hashicorp/errwrap v1.1.0 // indirect
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github.com/json-iterator/go v1.1.12 // indirect
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github.com/json-iterator/go v1.1.12 // indirect
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github.com/klauspost/cpuid/v2 v2.0.4 // indirect
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github.com/klauspost/cpuid/v2 v2.2.5 // indirect
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github.com/matttproud/golang_protobuf_extensions v1.0.4 // indirect
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github.com/matttproud/golang_protobuf_extensions v1.0.4 // indirect
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github.com/miekg/pkcs11 v1.1.1 // indirect
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github.com/miekg/pkcs11 v1.1.1 // indirect
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github.com/mistifyio/go-zfs/v3 v3.0.1 // indirect
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github.com/mistifyio/go-zfs/v3 v3.0.1 // indirect
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9
go.sum
9
go.sum
@ -648,8 +648,8 @@ github.com/klauspost/compress v1.11.3/go.mod h1:aoV0uJVorq1K+umq18yTdKaF57EivdYs
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github.com/klauspost/compress v1.11.13/go.mod h1:aoV0uJVorq1K+umq18yTdKaF57EivdYsUV+/s2qKfXs=
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github.com/klauspost/compress v1.11.13/go.mod h1:aoV0uJVorq1K+umq18yTdKaF57EivdYsUV+/s2qKfXs=
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github.com/klauspost/compress v1.16.7 h1:2mk3MPGNzKyxErAw8YaohYh69+pa4sIQSC0fPGCFR9I=
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github.com/klauspost/compress v1.16.7 h1:2mk3MPGNzKyxErAw8YaohYh69+pa4sIQSC0fPGCFR9I=
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github.com/klauspost/compress v1.16.7/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/compress v1.16.7/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/cpuid/v2 v2.0.4 h1:g0I61F2K2DjRHz1cnxlkNSBIaePVoJIjjnHui8QHbiw=
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github.com/klauspost/cpuid/v2 v2.2.5 h1:0E5MSMDEoAulmXNFquVs//DdoomxaoTY1kUhbc/qbZg=
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github.com/klauspost/cpuid/v2 v2.0.4/go.mod h1:FInQzS24/EEf25PyTYn52gqo7WaD8xa0213Md/qVLRg=
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github.com/klauspost/cpuid/v2 v2.2.5/go.mod h1:Lcz8mBdAVJIBVzewtcLocK12l3Y+JytZYpaMropDUws=
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github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.2/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.2/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.3/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.3/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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@ -689,8 +689,8 @@ github.com/miekg/dns v1.0.14/go.mod h1:W1PPwlIAgtquWBMBEV9nkV9Cazfe8ScdGz/Lj7v3N
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github.com/miekg/pkcs11 v1.0.3/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
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github.com/miekg/pkcs11 v1.0.3/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
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github.com/miekg/pkcs11 v1.1.1 h1:Ugu9pdy6vAYku5DEpVWVFPYnzV+bxB+iRdbuFSu7TvU=
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github.com/miekg/pkcs11 v1.1.1 h1:Ugu9pdy6vAYku5DEpVWVFPYnzV+bxB+iRdbuFSu7TvU=
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github.com/miekg/pkcs11 v1.1.1/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
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github.com/miekg/pkcs11 v1.1.1/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
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github.com/minio/sha256-simd v1.0.0 h1:v1ta+49hkWZyvaKwrQB8elexRqm6Y0aMLjCNsrYxo6g=
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github.com/minio/sha256-simd v1.0.1 h1:6kaan5IFmwTNynnKKpDHe6FWHohJOHhCPchzK49dzMM=
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github.com/minio/sha256-simd v1.0.0/go.mod h1:OuYzVNI5vcoYIAmbIvHPl3N3jUzVedXbKy5RFepssQM=
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github.com/minio/sha256-simd v1.0.1/go.mod h1:Pz6AKMiUdngCLpeTL/RJY1M9rUuPMYujV5xJjtbRSN8=
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github.com/mistifyio/go-zfs v2.1.2-0.20190413222219-f784269be439+incompatible/go.mod h1:8AuVvqP/mXw1px98n46wfvcGfQ4ci2FwoAjKYxuo3Z4=
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github.com/mistifyio/go-zfs v2.1.2-0.20190413222219-f784269be439+incompatible/go.mod h1:8AuVvqP/mXw1px98n46wfvcGfQ4ci2FwoAjKYxuo3Z4=
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github.com/mistifyio/go-zfs/v3 v3.0.1 h1:YaoXgBePoMA12+S1u/ddkv+QqxcfiZK4prI6HPnkFiU=
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github.com/mistifyio/go-zfs/v3 v3.0.1 h1:YaoXgBePoMA12+S1u/ddkv+QqxcfiZK4prI6HPnkFiU=
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github.com/mistifyio/go-zfs/v3 v3.0.1/go.mod h1:CzVgeB0RvF2EGzQnytKVvVSDwmKJXxkOTUGbNrTja/k=
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github.com/mistifyio/go-zfs/v3 v3.0.1/go.mod h1:CzVgeB0RvF2EGzQnytKVvVSDwmKJXxkOTUGbNrTja/k=
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@ -1324,6 +1324,7 @@ golang.org/x/sys v0.0.0-20220715151400-c0bba94af5f8/go.mod h1:oPkhp1MJrh7nUepCBc
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golang.org/x/sys v0.0.0-20220908164124-27713097b956/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.0.0-20220908164124-27713097b956/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.1.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.1.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.2.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.2.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.5.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.10.0 h1:SqMFp9UcQJZa+pmYuAKjd9xq1f0j5rLcDIk0mj4qAsA=
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golang.org/x/sys v0.10.0 h1:SqMFp9UcQJZa+pmYuAKjd9xq1f0j5rLcDIk0mj4qAsA=
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golang.org/x/sys v0.10.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/sys v0.10.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
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golang.org/x/term v0.0.0-20201117132131-f5c789dd3221/go.mod h1:Nr5EML6q2oocZ2LXRh80K7BxOlk5/8JxuGnuhpl+muw=
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golang.org/x/term v0.0.0-20201117132131-f5c789dd3221/go.mod h1:Nr5EML6q2oocZ2LXRh80K7BxOlk5/8JxuGnuhpl+muw=
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@ -1285,8 +1285,9 @@ github.com/klauspost/compress v1.16.0/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQs
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github.com/klauspost/compress v1.16.5/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/compress v1.16.5/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/compress v1.16.7 h1:2mk3MPGNzKyxErAw8YaohYh69+pa4sIQSC0fPGCFR9I=
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github.com/klauspost/compress v1.16.7 h1:2mk3MPGNzKyxErAw8YaohYh69+pa4sIQSC0fPGCFR9I=
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github.com/klauspost/compress v1.16.7/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/compress v1.16.7/go.mod h1:ntbaceVETuRiXiv4DpjP66DpAtAGkEQskQzEyD//IeE=
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github.com/klauspost/cpuid/v2 v2.0.4/go.mod h1:FInQzS24/EEf25PyTYn52gqo7WaD8xa0213Md/qVLRg=
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github.com/klauspost/cpuid/v2 v2.0.9/go.mod h1:FInQzS24/EEf25PyTYn52gqo7WaD8xa0213Md/qVLRg=
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github.com/klauspost/cpuid/v2 v2.0.9/go.mod h1:FInQzS24/EEf25PyTYn52gqo7WaD8xa0213Md/qVLRg=
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github.com/klauspost/cpuid/v2 v2.2.3/go.mod h1:RVVoqg1df56z8g3pUjL/3lE5UfnlrJX8tyFgg4nqhuY=
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github.com/klauspost/cpuid/v2 v2.2.5/go.mod h1:Lcz8mBdAVJIBVzewtcLocK12l3Y+JytZYpaMropDUws=
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github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.2/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.2/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.3/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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github.com/konsorten/go-windows-terminal-sequences v1.0.3/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=
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@ -1341,7 +1342,7 @@ github.com/miekg/dns v1.1.43/go.mod h1:+evo5L0630/F6ca/Z9+GAqzhjGyn8/c+TBaOyfEl0
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github.com/miekg/pkcs11 v1.1.1/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
|
github.com/miekg/pkcs11 v1.1.1/go.mod h1:XsNlhZGX73bx86s2hdc/FuaLm2CPZJemRLMA+WTFxgs=
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github.com/minio/asm2plan9s v0.0.0-20200509001527-cdd76441f9d8/go.mod h1:mC1jAcsrzbxHt8iiaC+zU4b1ylILSosueou12R++wfY=
|
github.com/minio/asm2plan9s v0.0.0-20200509001527-cdd76441f9d8/go.mod h1:mC1jAcsrzbxHt8iiaC+zU4b1ylILSosueou12R++wfY=
|
||||||
github.com/minio/c2goasm v0.0.0-20190812172519-36a3d3bbc4f3/go.mod h1:RagcQ7I8IeTMnF8JTXieKnO4Z6JCsikNEzj0DwauVzE=
|
github.com/minio/c2goasm v0.0.0-20190812172519-36a3d3bbc4f3/go.mod h1:RagcQ7I8IeTMnF8JTXieKnO4Z6JCsikNEzj0DwauVzE=
|
||||||
github.com/minio/sha256-simd v1.0.0/go.mod h1:OuYzVNI5vcoYIAmbIvHPl3N3jUzVedXbKy5RFepssQM=
|
github.com/minio/sha256-simd v1.0.1/go.mod h1:Pz6AKMiUdngCLpeTL/RJY1M9rUuPMYujV5xJjtbRSN8=
|
||||||
github.com/mistifyio/go-zfs/v3 v3.0.1/go.mod h1:CzVgeB0RvF2EGzQnytKVvVSDwmKJXxkOTUGbNrTja/k=
|
github.com/mistifyio/go-zfs/v3 v3.0.1/go.mod h1:CzVgeB0RvF2EGzQnytKVvVSDwmKJXxkOTUGbNrTja/k=
|
||||||
github.com/mitchellh/cli v1.0.0/go.mod h1:hNIlj7HEI86fIcpObd7a0FcrxTWetlwJDGcceTlRvqc=
|
github.com/mitchellh/cli v1.0.0/go.mod h1:hNIlj7HEI86fIcpObd7a0FcrxTWetlwJDGcceTlRvqc=
|
||||||
github.com/mitchellh/go-homedir v1.0.0/go.mod h1:SfyaCUpYCn1Vlf4IUYiD9fPX4A5wJrkLzIz1N1q0pr0=
|
github.com/mitchellh/go-homedir v1.0.0/go.mod h1:SfyaCUpYCn1Vlf4IUYiD9fPX4A5wJrkLzIz1N1q0pr0=
|
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@ -2044,6 +2045,7 @@ golang.org/x/sys v0.0.0-20220520151302-bc2c85ada10a/go.mod h1:oPkhp1MJrh7nUepCBc
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golang.org/x/sys v0.0.0-20220610221304-9f5ed59c137d/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220610221304-9f5ed59c137d/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
golang.org/x/sys v0.0.0-20220615213510-4f61da869c0c/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220615213510-4f61da869c0c/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
golang.org/x/sys v0.0.0-20220624220833-87e55d714810/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220624220833-87e55d714810/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
|
golang.org/x/sys v0.0.0-20220704084225-05e143d24a9e/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
golang.org/x/sys v0.0.0-20220715151400-c0bba94af5f8/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220715151400-c0bba94af5f8/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
golang.org/x/sys v0.0.0-20220722155257-8c9f86f7a55f/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220722155257-8c9f86f7a55f/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
golang.org/x/sys v0.0.0-20220728004956-3c1f35247d10/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
golang.org/x/sys v0.0.0-20220728004956-3c1f35247d10/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=
|
||||||
|
|||||||
74
vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
generated
vendored
Normal file
74
vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
generated
vendored
Normal file
@ -0,0 +1,74 @@
|
|||||||
|
# This is an example goreleaser.yaml file with some sane defaults.
|
||||||
|
# Make sure to check the documentation at http://goreleaser.com
|
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|
|
||||||
|
builds:
|
||||||
|
-
|
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|
id: "cpuid"
|
||||||
|
binary: cpuid
|
||||||
|
main: ./cmd/cpuid/main.go
|
||||||
|
env:
|
||||||
|
- CGO_ENABLED=0
|
||||||
|
flags:
|
||||||
|
- -ldflags=-s -w
|
||||||
|
goos:
|
||||||
|
- aix
|
||||||
|
- linux
|
||||||
|
- freebsd
|
||||||
|
- netbsd
|
||||||
|
- windows
|
||||||
|
- darwin
|
||||||
|
goarch:
|
||||||
|
- 386
|
||||||
|
- amd64
|
||||||
|
- arm64
|
||||||
|
goarm:
|
||||||
|
- 7
|
||||||
|
|
||||||
|
archives:
|
||||||
|
-
|
||||||
|
id: cpuid
|
||||||
|
name_template: "cpuid-{{ .Os }}_{{ .Arch }}_{{ .Version }}"
|
||||||
|
replacements:
|
||||||
|
aix: AIX
|
||||||
|
darwin: OSX
|
||||||
|
linux: Linux
|
||||||
|
windows: Windows
|
||||||
|
386: i386
|
||||||
|
amd64: x86_64
|
||||||
|
freebsd: FreeBSD
|
||||||
|
netbsd: NetBSD
|
||||||
|
format_overrides:
|
||||||
|
- goos: windows
|
||||||
|
format: zip
|
||||||
|
files:
|
||||||
|
- LICENSE
|
||||||
|
checksum:
|
||||||
|
name_template: 'checksums.txt'
|
||||||
|
snapshot:
|
||||||
|
name_template: "{{ .Tag }}-next"
|
||||||
|
changelog:
|
||||||
|
sort: asc
|
||||||
|
filters:
|
||||||
|
exclude:
|
||||||
|
- '^doc:'
|
||||||
|
- '^docs:'
|
||||||
|
- '^test:'
|
||||||
|
- '^tests:'
|
||||||
|
- '^Update\sREADME.md'
|
||||||
|
|
||||||
|
nfpms:
|
||||||
|
-
|
||||||
|
file_name_template: "cpuid_package_{{ .Version }}_{{ .Os }}_{{ .Arch }}"
|
||||||
|
vendor: Klaus Post
|
||||||
|
homepage: https://github.com/klauspost/cpuid
|
||||||
|
maintainer: Klaus Post <klauspost@gmail.com>
|
||||||
|
description: CPUID Tool
|
||||||
|
license: BSD 3-Clause
|
||||||
|
formats:
|
||||||
|
- deb
|
||||||
|
- rpm
|
||||||
|
replacements:
|
||||||
|
darwin: Darwin
|
||||||
|
linux: Linux
|
||||||
|
freebsd: FreeBSD
|
||||||
|
amd64: x86_64
|
||||||
56
vendor/github.com/klauspost/cpuid/v2/.travis.yml
generated
vendored
56
vendor/github.com/klauspost/cpuid/v2/.travis.yml
generated
vendored
@ -1,56 +0,0 @@
|
|||||||
language: go
|
|
||||||
|
|
||||||
os:
|
|
||||||
- linux
|
|
||||||
- osx
|
|
||||||
- windows
|
|
||||||
|
|
||||||
arch:
|
|
||||||
- amd64
|
|
||||||
- arm64
|
|
||||||
|
|
||||||
go:
|
|
||||||
- 1.13.x
|
|
||||||
- 1.14.x
|
|
||||||
- 1.15.x
|
|
||||||
- 1.16.x
|
|
||||||
- master
|
|
||||||
|
|
||||||
script:
|
|
||||||
- go vet ./...
|
|
||||||
- go test -test.v -test.run ^TestCPUID$
|
|
||||||
- go test -race ./...
|
|
||||||
- go test -tags=noasm ./...
|
|
||||||
|
|
||||||
matrix:
|
|
||||||
allow_failures:
|
|
||||||
- go: 'master'
|
|
||||||
fast_finish: true
|
|
||||||
include:
|
|
||||||
- stage: gofmt
|
|
||||||
go: 1.15.x
|
|
||||||
os: linux
|
|
||||||
arch: amd64
|
|
||||||
script:
|
|
||||||
- diff <(gofmt -d .) <(printf "")
|
|
||||||
- diff <(gofmt -d ./private) <(printf "")
|
|
||||||
- go install github.com/klauspost/asmfmt/cmd/asmfmt
|
|
||||||
- diff <(asmfmt -d .) <(printf "")
|
|
||||||
- stage: i386
|
|
||||||
go: 1.15.x
|
|
||||||
os: linux
|
|
||||||
arch: amd64
|
|
||||||
script:
|
|
||||||
- GOOS=linux GOARCH=386 go test .
|
|
||||||
- stage: buildotherprev
|
|
||||||
go: 1.15.x
|
|
||||||
os: linux
|
|
||||||
arch: amd64
|
|
||||||
script:
|
|
||||||
- ./test-architectures.sh
|
|
||||||
- stage: buildother
|
|
||||||
go: 1.16.x
|
|
||||||
os: linux
|
|
||||||
arch: amd64
|
|
||||||
script:
|
|
||||||
- ./test-architectures.sh
|
|
||||||
364
vendor/github.com/klauspost/cpuid/v2/README.md
generated
vendored
364
vendor/github.com/klauspost/cpuid/v2/README.md
generated
vendored
@ -17,9 +17,22 @@ Package home: https://github.com/klauspost/cpuid
|
|||||||
## installing
|
## installing
|
||||||
|
|
||||||
`go get -u github.com/klauspost/cpuid/v2` using modules.
|
`go get -u github.com/klauspost/cpuid/v2` using modules.
|
||||||
|
|
||||||
Drop `v2` for others.
|
Drop `v2` for others.
|
||||||
|
|
||||||
|
Installing binary:
|
||||||
|
|
||||||
|
`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`
|
||||||
|
|
||||||
|
Or download binaries from release page: https://github.com/klauspost/cpuid/releases
|
||||||
|
|
||||||
|
### Homebrew
|
||||||
|
|
||||||
|
For macOS/Linux users, you can install via [brew](https://brew.sh/)
|
||||||
|
|
||||||
|
```sh
|
||||||
|
$ brew install cpuid
|
||||||
|
```
|
||||||
|
|
||||||
## example
|
## example
|
||||||
|
|
||||||
```Go
|
```Go
|
||||||
@ -39,10 +52,10 @@ func main() {
|
|||||||
fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore)
|
fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore)
|
||||||
fmt.Println("LogicalCores:", CPU.LogicalCores)
|
fmt.Println("LogicalCores:", CPU.LogicalCores)
|
||||||
fmt.Println("Family", CPU.Family, "Model:", CPU.Model, "Vendor ID:", CPU.VendorID)
|
fmt.Println("Family", CPU.Family, "Model:", CPU.Model, "Vendor ID:", CPU.VendorID)
|
||||||
fmt.Println("Features:", fmt.Sprintf(strings.Join(CPU.FeatureSet(), ",")))
|
fmt.Println("Features:", strings.Join(CPU.FeatureSet(), ","))
|
||||||
fmt.Println("Cacheline bytes:", CPU.CacheLine)
|
fmt.Println("Cacheline bytes:", CPU.CacheLine)
|
||||||
fmt.Println("L1 Data Cache:", CPU.Cache.L1D, "bytes")
|
fmt.Println("L1 Data Cache:", CPU.Cache.L1D, "bytes")
|
||||||
fmt.Println("L1 Instruction Cache:", CPU.Cache.L1D, "bytes")
|
fmt.Println("L1 Instruction Cache:", CPU.Cache.L1I, "bytes")
|
||||||
fmt.Println("L2 Cache:", CPU.Cache.L2, "bytes")
|
fmt.Println("L2 Cache:", CPU.Cache.L2, "bytes")
|
||||||
fmt.Println("L3 Cache:", CPU.Cache.L3, "bytes")
|
fmt.Println("L3 Cache:", CPU.Cache.L3, "bytes")
|
||||||
fmt.Println("Frequency", CPU.Hz, "hz")
|
fmt.Println("Frequency", CPU.Hz, "hz")
|
||||||
@ -77,10 +90,14 @@ We have Streaming SIMD 2 Extensions
|
|||||||
The `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features.
|
The `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features.
|
||||||
A faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler.
|
A faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler.
|
||||||
|
|
||||||
|
To test a larger number of features, they can be combined using `f := CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)`, etc.
|
||||||
|
This can be using with `cpuid.CPU.HasAll(f)` to quickly test if all features are supported.
|
||||||
|
|
||||||
Note that for some cpu/os combinations some features will not be detected.
|
Note that for some cpu/os combinations some features will not be detected.
|
||||||
`amd64` has rather good support and should work reliably on all platforms.
|
`amd64` has rather good support and should work reliably on all platforms.
|
||||||
|
|
||||||
Note that hypervisors may not pass through all CPU features.
|
Note that hypervisors may not pass through all CPU features through to the guest OS,
|
||||||
|
so even if your host supports a feature it may not be visible on guests.
|
||||||
|
|
||||||
## arm64 feature detection
|
## arm64 feature detection
|
||||||
|
|
||||||
@ -132,6 +149,345 @@ func main() {
|
|||||||
}
|
}
|
||||||
```
|
```
|
||||||
|
|
||||||
|
## commandline
|
||||||
|
|
||||||
|
Download as binary from: https://github.com/klauspost/cpuid/releases
|
||||||
|
|
||||||
|
Install from source:
|
||||||
|
|
||||||
|
`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`
|
||||||
|
|
||||||
|
### Example
|
||||||
|
|
||||||
|
```
|
||||||
|
λ cpuid
|
||||||
|
Name: AMD Ryzen 9 3950X 16-Core Processor
|
||||||
|
Vendor String: AuthenticAMD
|
||||||
|
Vendor ID: AMD
|
||||||
|
PhysicalCores: 16
|
||||||
|
Threads Per Core: 2
|
||||||
|
Logical Cores: 32
|
||||||
|
CPU Family 23 Model: 113
|
||||||
|
Features: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CLZERO,CMOV,CMPXCHG8,CPBOOST,CX16,F16C,FMA3,FXSR,FXSROPT,HTT,HYPERVISOR,LAHF,LZCNT,MCAOVERFLOW,MMX,MMXEXT,MOVBE,NX,OSXSAVE,POPCNT,RDRAND,RDSEED,RDTSCP,SCE,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3,SUCCOR,X87,XSAVE
|
||||||
|
Microarchitecture level: 3
|
||||||
|
Cacheline bytes: 64
|
||||||
|
L1 Instruction Cache: 32768 bytes
|
||||||
|
L1 Data Cache: 32768 bytes
|
||||||
|
L2 Cache: 524288 bytes
|
||||||
|
L3 Cache: 16777216 bytes
|
||||||
|
|
||||||
|
```
|
||||||
|
### JSON Output:
|
||||||
|
|
||||||
|
```
|
||||||
|
λ cpuid --json
|
||||||
|
{
|
||||||
|
"BrandName": "AMD Ryzen 9 3950X 16-Core Processor",
|
||||||
|
"VendorID": 2,
|
||||||
|
"VendorString": "AuthenticAMD",
|
||||||
|
"PhysicalCores": 16,
|
||||||
|
"ThreadsPerCore": 2,
|
||||||
|
"LogicalCores": 32,
|
||||||
|
"Family": 23,
|
||||||
|
"Model": 113,
|
||||||
|
"CacheLine": 64,
|
||||||
|
"Hz": 0,
|
||||||
|
"BoostFreq": 0,
|
||||||
|
"Cache": {
|
||||||
|
"L1I": 32768,
|
||||||
|
"L1D": 32768,
|
||||||
|
"L2": 524288,
|
||||||
|
"L3": 16777216
|
||||||
|
},
|
||||||
|
"SGX": {
|
||||||
|
"Available": false,
|
||||||
|
"LaunchControl": false,
|
||||||
|
"SGX1Supported": false,
|
||||||
|
"SGX2Supported": false,
|
||||||
|
"MaxEnclaveSizeNot64": 0,
|
||||||
|
"MaxEnclaveSize64": 0,
|
||||||
|
"EPCSections": null
|
||||||
|
},
|
||||||
|
"Features": [
|
||||||
|
"ADX",
|
||||||
|
"AESNI",
|
||||||
|
"AVX",
|
||||||
|
"AVX2",
|
||||||
|
"BMI1",
|
||||||
|
"BMI2",
|
||||||
|
"CLMUL",
|
||||||
|
"CLZERO",
|
||||||
|
"CMOV",
|
||||||
|
"CMPXCHG8",
|
||||||
|
"CPBOOST",
|
||||||
|
"CX16",
|
||||||
|
"F16C",
|
||||||
|
"FMA3",
|
||||||
|
"FXSR",
|
||||||
|
"FXSROPT",
|
||||||
|
"HTT",
|
||||||
|
"HYPERVISOR",
|
||||||
|
"LAHF",
|
||||||
|
"LZCNT",
|
||||||
|
"MCAOVERFLOW",
|
||||||
|
"MMX",
|
||||||
|
"MMXEXT",
|
||||||
|
"MOVBE",
|
||||||
|
"NX",
|
||||||
|
"OSXSAVE",
|
||||||
|
"POPCNT",
|
||||||
|
"RDRAND",
|
||||||
|
"RDSEED",
|
||||||
|
"RDTSCP",
|
||||||
|
"SCE",
|
||||||
|
"SHA",
|
||||||
|
"SSE",
|
||||||
|
"SSE2",
|
||||||
|
"SSE3",
|
||||||
|
"SSE4",
|
||||||
|
"SSE42",
|
||||||
|
"SSE4A",
|
||||||
|
"SSSE3",
|
||||||
|
"SUCCOR",
|
||||||
|
"X87",
|
||||||
|
"XSAVE"
|
||||||
|
],
|
||||||
|
"X64Level": 3
|
||||||
|
}
|
||||||
|
```
|
||||||
|
|
||||||
|
### Check CPU microarch level
|
||||||
|
|
||||||
|
```
|
||||||
|
λ cpuid --check-level=3
|
||||||
|
2022/03/18 17:04:40 AMD Ryzen 9 3950X 16-Core Processor
|
||||||
|
2022/03/18 17:04:40 Microarchitecture level 3 is supported. Max level is 3.
|
||||||
|
Exit Code 0
|
||||||
|
|
||||||
|
λ cpuid --check-level=4
|
||||||
|
2022/03/18 17:06:18 AMD Ryzen 9 3950X 16-Core Processor
|
||||||
|
2022/03/18 17:06:18 Microarchitecture level 4 not supported. Max level is 3.
|
||||||
|
Exit Code 1
|
||||||
|
```
|
||||||
|
|
||||||
|
|
||||||
|
## Available flags
|
||||||
|
|
||||||
|
### x86 & amd64
|
||||||
|
|
||||||
|
| Feature Flag | Description |
|
||||||
|
|--------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
|
||||||
|
| ADX | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) |
|
||||||
|
| AESNI | Advanced Encryption Standard New Instructions |
|
||||||
|
| AMD3DNOW | AMD 3DNOW |
|
||||||
|
| AMD3DNOWEXT | AMD 3DNowExt |
|
||||||
|
| AMXBF16 | Tile computational operations on BFLOAT16 numbers |
|
||||||
|
| AMXINT8 | Tile computational operations on 8-bit integers |
|
||||||
|
| AMXFP16 | Tile computational operations on FP16 numbers |
|
||||||
|
| AMXTILE | Tile architecture |
|
||||||
|
| AVX | AVX functions |
|
||||||
|
| AVX2 | AVX2 functions |
|
||||||
|
| AVX512BF16 | AVX-512 BFLOAT16 Instructions |
|
||||||
|
| AVX512BITALG | AVX-512 Bit Algorithms |
|
||||||
|
| AVX512BW | AVX-512 Byte and Word Instructions |
|
||||||
|
| AVX512CD | AVX-512 Conflict Detection Instructions |
|
||||||
|
| AVX512DQ | AVX-512 Doubleword and Quadword Instructions |
|
||||||
|
| AVX512ER | AVX-512 Exponential and Reciprocal Instructions |
|
||||||
|
| AVX512F | AVX-512 Foundation |
|
||||||
|
| AVX512FP16 | AVX-512 FP16 Instructions |
|
||||||
|
| AVX512IFMA | AVX-512 Integer Fused Multiply-Add Instructions |
|
||||||
|
| AVX512PF | AVX-512 Prefetch Instructions |
|
||||||
|
| AVX512VBMI | AVX-512 Vector Bit Manipulation Instructions |
|
||||||
|
| AVX512VBMI2 | AVX-512 Vector Bit Manipulation Instructions, Version 2 |
|
||||||
|
| AVX512VL | AVX-512 Vector Length Extensions |
|
||||||
|
| AVX512VNNI | AVX-512 Vector Neural Network Instructions |
|
||||||
|
| AVX512VP2INTERSECT | AVX-512 Intersect for D/Q |
|
||||||
|
| AVX512VPOPCNTDQ | AVX-512 Vector Population Count Doubleword and Quadword |
|
||||||
|
| AVXIFMA | AVX-IFMA instructions |
|
||||||
|
| AVXNECONVERT | AVX-NE-CONVERT instructions |
|
||||||
|
| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |
|
||||||
|
| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |
|
||||||
|
| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |
|
||||||
|
| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 |
|
||||||
|
| BMI1 | Bit Manipulation Instruction Set 1 |
|
||||||
|
| BMI2 | Bit Manipulation Instruction Set 2 |
|
||||||
|
| CETIBT | Intel CET Indirect Branch Tracking |
|
||||||
|
| CETSS | Intel CET Shadow Stack |
|
||||||
|
| CLDEMOTE | Cache Line Demote |
|
||||||
|
| CLMUL | Carry-less Multiplication |
|
||||||
|
| CLZERO | CLZERO instruction supported |
|
||||||
|
| CMOV | i686 CMOV |
|
||||||
|
| CMPCCXADD | CMPCCXADD instructions |
|
||||||
|
| CMPSB_SCADBS_SHORT | Fast short CMPSB and SCASB |
|
||||||
|
| CMPXCHG8 | CMPXCHG8 instruction |
|
||||||
|
| CPBOOST | Core Performance Boost |
|
||||||
|
| CPPC | AMD: Collaborative Processor Performance Control |
|
||||||
|
| CX16 | CMPXCHG16B Instruction |
|
||||||
|
| EFER_LMSLE_UNS | AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ |
|
||||||
|
| ENQCMD | Enqueue Command |
|
||||||
|
| ERMS | Enhanced REP MOVSB/STOSB |
|
||||||
|
| F16C | Half-precision floating-point conversion |
|
||||||
|
| FLUSH_L1D | Flush L1D cache |
|
||||||
|
| FMA3 | Intel FMA 3. Does not imply AVX. |
|
||||||
|
| FMA4 | Bulldozer FMA4 functions |
|
||||||
|
| FP128 | AMD: When set, the internal FP/SIMD execution datapath is 128-bits wide |
|
||||||
|
| FP256 | AMD: When set, the internal FP/SIMD execution datapath is 256-bits wide |
|
||||||
|
| FSRM | Fast Short Rep Mov |
|
||||||
|
| FXSR | FXSAVE, FXRESTOR instructions, CR4 bit 9 |
|
||||||
|
| FXSROPT | FXSAVE/FXRSTOR optimizations |
|
||||||
|
| GFNI | Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. |
|
||||||
|
| HLE | Hardware Lock Elision |
|
||||||
|
| HRESET | If set CPU supports history reset and the IA32_HRESET_ENABLE MSR |
|
||||||
|
| HTT | Hyperthreading (enabled) |
|
||||||
|
| HWA | Hardware assert supported. Indicates support for MSRC001_10 |
|
||||||
|
| HYBRID_CPU | This part has CPUs of more than one type. |
|
||||||
|
| HYPERVISOR | This bit has been reserved by Intel & AMD for use by hypervisors |
|
||||||
|
| IA32_ARCH_CAP | IA32_ARCH_CAPABILITIES MSR (Intel) |
|
||||||
|
| IA32_CORE_CAP | IA32_CORE_CAPABILITIES MSR |
|
||||||
|
| IBPB | Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) |
|
||||||
|
| IBRS | AMD: Indirect Branch Restricted Speculation |
|
||||||
|
| IBRS_PREFERRED | AMD: IBRS is preferred over software solution |
|
||||||
|
| IBRS_PROVIDES_SMP | AMD: IBRS provides Same Mode Protection |
|
||||||
|
| IBS | Instruction Based Sampling (AMD) |
|
||||||
|
| IBSBRNTRGT | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSFETCHSAM | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSFFV | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSOPCNT | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSOPCNTEXT | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSOPSAM | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSRDWROPCNT | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBSRIPINVALIDCHK | Instruction Based Sampling Feature (AMD) |
|
||||||
|
| IBS_FETCH_CTLX | AMD: IBS fetch control extended MSR supported |
|
||||||
|
| IBS_OPDATA4 | AMD: IBS op data 4 MSR supported |
|
||||||
|
| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |
|
||||||
|
| IBS_PREVENTHOST | Disallowing IBS use by the host supported |
|
||||||
|
| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |
|
||||||
|
| IDPRED_CTRL | IPRED_DIS |
|
||||||
|
| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |
|
||||||
|
| INVLPGB | NVLPGB and TLBSYNC instruction supported |
|
||||||
|
| LAHF | LAHF/SAHF in long mode |
|
||||||
|
| LAM | If set, CPU supports Linear Address Masking |
|
||||||
|
| LBRVIRT | LBR virtualization |
|
||||||
|
| LZCNT | LZCNT instruction |
|
||||||
|
| MCAOVERFLOW | MCA overflow recovery support. |
|
||||||
|
| MCDT_NO | Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. |
|
||||||
|
| MCOMMIT | MCOMMIT instruction supported |
|
||||||
|
| MD_CLEAR | VERW clears CPU buffers |
|
||||||
|
| MMX | standard MMX |
|
||||||
|
| MMXEXT | SSE integer functions or AMD MMX ext |
|
||||||
|
| MOVBE | MOVBE instruction (big-endian) |
|
||||||
|
| MOVDIR64B | Move 64 Bytes as Direct Store |
|
||||||
|
| MOVDIRI | Move Doubleword as Direct Store |
|
||||||
|
| MOVSB_ZL | Fast Zero-Length MOVSB |
|
||||||
|
| MPX | Intel MPX (Memory Protection Extensions) |
|
||||||
|
| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD |
|
||||||
|
| MSRIRC | Instruction Retired Counter MSR available |
|
||||||
|
| MSRLIST | Read/Write List of Model Specific Registers |
|
||||||
|
| MSR_PAGEFLUSH | Page Flush MSR available |
|
||||||
|
| NRIPS | Indicates support for NRIP save on VMEXIT |
|
||||||
|
| NX | NX (No-Execute) bit |
|
||||||
|
| OSXSAVE | XSAVE enabled by OS |
|
||||||
|
| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |
|
||||||
|
| POPCNT | POPCNT instruction |
|
||||||
|
| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |
|
||||||
|
| PREFETCHI | PREFETCHIT0/1 instructions |
|
||||||
|
| PSFD | Predictive Store Forward Disable |
|
||||||
|
| RDPRU | RDPRU instruction supported |
|
||||||
|
| RDRAND | RDRAND instruction is available |
|
||||||
|
| RDSEED | RDSEED instruction is available |
|
||||||
|
| RDTSCP | RDTSCP Instruction |
|
||||||
|
| RRSBA_CTRL | Restricted RSB Alternate |
|
||||||
|
| RTM | Restricted Transactional Memory |
|
||||||
|
| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |
|
||||||
|
| SERIALIZE | Serialize Instruction Execution |
|
||||||
|
| SEV | AMD Secure Encrypted Virtualization supported |
|
||||||
|
| SEV_64BIT | AMD SEV guest execution only allowed from a 64-bit host |
|
||||||
|
| SEV_ALTERNATIVE | AMD SEV Alternate Injection supported |
|
||||||
|
| SEV_DEBUGSWAP | Full debug state swap supported for SEV-ES guests |
|
||||||
|
| SEV_ES | AMD SEV Encrypted State supported |
|
||||||
|
| SEV_RESTRICTED | AMD SEV Restricted Injection supported |
|
||||||
|
| SEV_SNP | AMD SEV Secure Nested Paging supported |
|
||||||
|
| SGX | Software Guard Extensions |
|
||||||
|
| SGXLC | Software Guard Extensions Launch Control |
|
||||||
|
| SHA | Intel SHA Extensions |
|
||||||
|
| SME | AMD Secure Memory Encryption supported |
|
||||||
|
| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced |
|
||||||
|
| SPEC_CTRL_SSBD | Speculative Store Bypass Disable |
|
||||||
|
| SRBDS_CTRL | SRBDS mitigation MSR available |
|
||||||
|
| SSE | SSE functions |
|
||||||
|
| SSE2 | P4 SSE functions |
|
||||||
|
| SSE3 | Prescott SSE3 functions |
|
||||||
|
| SSE4 | Penryn SSE4.1 functions |
|
||||||
|
| SSE42 | Nehalem SSE4.2 functions |
|
||||||
|
| SSE4A | AMD Barcelona microarchitecture SSE4a instructions |
|
||||||
|
| SSSE3 | Conroe SSSE3 functions |
|
||||||
|
| STIBP | Single Thread Indirect Branch Predictors |
|
||||||
|
| STIBP_ALWAYSON | AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On |
|
||||||
|
| STOSB_SHORT | Fast short STOSB |
|
||||||
|
| SUCCOR | Software uncorrectable error containment and recovery capability. |
|
||||||
|
| SVM | AMD Secure Virtual Machine |
|
||||||
|
| SVMDA | Indicates support for the SVM decode assists. |
|
||||||
|
| SVMFBASID | SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control |
|
||||||
|
| SVML | AMD SVM lock. Indicates support for SVM-Lock. |
|
||||||
|
| SVMNP | AMD SVM nested paging |
|
||||||
|
| SVMPF | SVM pause intercept filter. Indicates support for the pause intercept filter |
|
||||||
|
| SVMPFT | SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold |
|
||||||
|
| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. |
|
||||||
|
| SYSEE | SYSENTER and SYSEXIT instructions |
|
||||||
|
| TBM | AMD Trailing Bit Manipulation |
|
||||||
|
| TDX_GUEST | Intel Trust Domain Extensions Guest |
|
||||||
|
| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations |
|
||||||
|
| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
|
||||||
|
| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. |
|
||||||
|
| TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 |
|
||||||
|
| TSXLDTRK | Intel TSX Suspend Load Address Tracking |
|
||||||
|
| VAES | Vector AES. AVX(512) versions requires additional checks. |
|
||||||
|
| VMCBCLEAN | VMCB clean bits. Indicates support for VMCB clean bits. |
|
||||||
|
| VMPL | AMD VM Permission Levels supported |
|
||||||
|
| VMSA_REGPROT | AMD VMSA Register Protection supported |
|
||||||
|
| VMX | Virtual Machine Extensions |
|
||||||
|
| VPCLMULQDQ | Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. |
|
||||||
|
| VTE | AMD Virtual Transparent Encryption supported |
|
||||||
|
| WAITPKG | TPAUSE, UMONITOR, UMWAIT |
|
||||||
|
| WBNOINVD | Write Back and Do Not Invalidate Cache |
|
||||||
|
| WRMSRNS | Non-Serializing Write to Model Specific Register |
|
||||||
|
| X87 | FPU |
|
||||||
|
| XGETBV1 | Supports XGETBV with ECX = 1 |
|
||||||
|
| XOP | Bulldozer XOP functions |
|
||||||
|
| XSAVE | XSAVE, XRESTOR, XSETBV, XGETBV |
|
||||||
|
| XSAVEC | Supports XSAVEC and the compacted form of XRSTOR. |
|
||||||
|
| XSAVEOPT | XSAVEOPT available |
|
||||||
|
| XSAVES | Supports XSAVES/XRSTORS and IA32_XSS |
|
||||||
|
|
||||||
|
# ARM features:
|
||||||
|
|
||||||
|
| Feature Flag | Description |
|
||||||
|
|--------------|------------------------------------------------------------------|
|
||||||
|
| AESARM | AES instructions |
|
||||||
|
| ARMCPUID | Some CPU ID registers readable at user-level |
|
||||||
|
| ASIMD | Advanced SIMD |
|
||||||
|
| ASIMDDP | SIMD Dot Product |
|
||||||
|
| ASIMDHP | Advanced SIMD half-precision floating point |
|
||||||
|
| ASIMDRDM | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) |
|
||||||
|
| ATOMICS | Large System Extensions (LSE) |
|
||||||
|
| CRC32 | CRC32/CRC32C instructions |
|
||||||
|
| DCPOP | Data cache clean to Point of Persistence (DC CVAP) |
|
||||||
|
| EVTSTRM | Generic timer |
|
||||||
|
| FCMA | Floatin point complex number addition and multiplication |
|
||||||
|
| FP | Single-precision and double-precision floating point |
|
||||||
|
| FPHP | Half-precision floating point |
|
||||||
|
| GPA | Generic Pointer Authentication |
|
||||||
|
| JSCVT | Javascript-style double->int convert (FJCVTZS) |
|
||||||
|
| LRCPC | Weaker release consistency (LDAPR, etc) |
|
||||||
|
| PMULL | Polynomial Multiply instructions (PMULL/PMULL2) |
|
||||||
|
| SHA1 | SHA-1 instructions (SHA1C, etc) |
|
||||||
|
| SHA2 | SHA-2 instructions (SHA256H, etc) |
|
||||||
|
| SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) |
|
||||||
|
| SHA512 | SHA512 instructions |
|
||||||
|
| SM3 | SM3 instructions |
|
||||||
|
| SM4 | SM4 instructions |
|
||||||
|
| SVE | Scalable Vector Extension |
|
||||||
|
|
||||||
# license
|
# license
|
||||||
|
|
||||||
This code is published under an MIT license. See LICENSE file for more information.
|
This code is published under an MIT license. See LICENSE file for more information.
|
||||||
|
|||||||
506
vendor/github.com/klauspost/cpuid/v2/cpuid.go
generated
vendored
506
vendor/github.com/klauspost/cpuid/v2/cpuid.go
generated
vendored
@ -14,7 +14,9 @@ import (
|
|||||||
"flag"
|
"flag"
|
||||||
"fmt"
|
"fmt"
|
||||||
"math"
|
"math"
|
||||||
|
"math/bits"
|
||||||
"os"
|
"os"
|
||||||
|
"runtime"
|
||||||
"strings"
|
"strings"
|
||||||
)
|
)
|
||||||
|
|
||||||
@ -71,6 +73,7 @@ const (
|
|||||||
AMD3DNOW // AMD 3DNOW
|
AMD3DNOW // AMD 3DNOW
|
||||||
AMD3DNOWEXT // AMD 3DNowExt
|
AMD3DNOWEXT // AMD 3DNowExt
|
||||||
AMXBF16 // Tile computational operations on BFLOAT16 numbers
|
AMXBF16 // Tile computational operations on BFLOAT16 numbers
|
||||||
|
AMXFP16 // Tile computational operations on FP16 numbers
|
||||||
AMXINT8 // Tile computational operations on 8-bit integers
|
AMXINT8 // Tile computational operations on 8-bit integers
|
||||||
AMXTILE // Tile architecture
|
AMXTILE // Tile architecture
|
||||||
AVX // AVX functions
|
AVX // AVX functions
|
||||||
@ -82,6 +85,7 @@ const (
|
|||||||
AVX512DQ // AVX-512 Doubleword and Quadword Instructions
|
AVX512DQ // AVX-512 Doubleword and Quadword Instructions
|
||||||
AVX512ER // AVX-512 Exponential and Reciprocal Instructions
|
AVX512ER // AVX-512 Exponential and Reciprocal Instructions
|
||||||
AVX512F // AVX-512 Foundation
|
AVX512F // AVX-512 Foundation
|
||||||
|
AVX512FP16 // AVX-512 FP16 Instructions
|
||||||
AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
|
AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
|
||||||
AVX512PF // AVX-512 Prefetch Instructions
|
AVX512PF // AVX-512 Prefetch Instructions
|
||||||
AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
|
AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
|
||||||
@ -90,23 +94,51 @@ const (
|
|||||||
AVX512VNNI // AVX-512 Vector Neural Network Instructions
|
AVX512VNNI // AVX-512 Vector Neural Network Instructions
|
||||||
AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
|
AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
|
||||||
AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
|
AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
|
||||||
AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one.
|
AVXIFMA // AVX-IFMA instructions
|
||||||
|
AVXNECONVERT // AVX-NE-CONVERT instructions
|
||||||
|
AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
|
||||||
|
AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
|
||||||
|
AVXVNNIINT8 // AVX-VNNI-INT8 instructions
|
||||||
|
BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
|
||||||
BMI1 // Bit Manipulation Instruction Set 1
|
BMI1 // Bit Manipulation Instruction Set 1
|
||||||
BMI2 // Bit Manipulation Instruction Set 2
|
BMI2 // Bit Manipulation Instruction Set 2
|
||||||
|
CETIBT // Intel CET Indirect Branch Tracking
|
||||||
|
CETSS // Intel CET Shadow Stack
|
||||||
CLDEMOTE // Cache Line Demote
|
CLDEMOTE // Cache Line Demote
|
||||||
CLMUL // Carry-less Multiplication
|
CLMUL // Carry-less Multiplication
|
||||||
|
CLZERO // CLZERO instruction supported
|
||||||
CMOV // i686 CMOV
|
CMOV // i686 CMOV
|
||||||
|
CMPCCXADD // CMPCCXADD instructions
|
||||||
|
CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
|
||||||
|
CMPXCHG8 // CMPXCHG8 instruction
|
||||||
|
CPBOOST // Core Performance Boost
|
||||||
|
CPPC // AMD: Collaborative Processor Performance Control
|
||||||
CX16 // CMPXCHG16B Instruction
|
CX16 // CMPXCHG16B Instruction
|
||||||
|
EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
|
||||||
ENQCMD // Enqueue Command
|
ENQCMD // Enqueue Command
|
||||||
ERMS // Enhanced REP MOVSB/STOSB
|
ERMS // Enhanced REP MOVSB/STOSB
|
||||||
F16C // Half-precision floating-point conversion
|
F16C // Half-precision floating-point conversion
|
||||||
|
FLUSH_L1D // Flush L1D cache
|
||||||
FMA3 // Intel FMA 3. Does not imply AVX.
|
FMA3 // Intel FMA 3. Does not imply AVX.
|
||||||
FMA4 // Bulldozer FMA4 functions
|
FMA4 // Bulldozer FMA4 functions
|
||||||
GFNI // Galois Field New Instructions
|
FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
|
||||||
|
FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
|
||||||
|
FSRM // Fast Short Rep Mov
|
||||||
|
FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
|
||||||
|
FXSROPT // FXSAVE/FXRSTOR optimizations
|
||||||
|
GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
|
||||||
HLE // Hardware Lock Elision
|
HLE // Hardware Lock Elision
|
||||||
|
HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
|
||||||
HTT // Hyperthreading (enabled)
|
HTT // Hyperthreading (enabled)
|
||||||
|
HWA // Hardware assert supported. Indicates support for MSRC001_10
|
||||||
|
HYBRID_CPU // This part has CPUs of more than one type.
|
||||||
HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
|
HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
|
||||||
|
IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
|
||||||
|
IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
|
||||||
IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
|
IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
|
||||||
|
IBRS // AMD: Indirect Branch Restricted Speculation
|
||||||
|
IBRS_PREFERRED // AMD: IBRS is preferred over software solution
|
||||||
|
IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
|
||||||
IBS // Instruction Based Sampling (AMD)
|
IBS // Instruction Based Sampling (AMD)
|
||||||
IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
|
IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
|
||||||
IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
|
IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
|
||||||
@ -116,22 +148,63 @@ const (
|
|||||||
IBSOPSAM // Instruction Based Sampling Feature (AMD)
|
IBSOPSAM // Instruction Based Sampling Feature (AMD)
|
||||||
IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
|
IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
|
||||||
IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
|
IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
|
||||||
|
IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
|
||||||
|
IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
|
||||||
|
IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
|
||||||
|
IBS_PREVENTHOST // Disallowing IBS use by the host supported
|
||||||
|
IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
|
||||||
|
IDPRED_CTRL // IPRED_DIS
|
||||||
|
INT_WBINVD // WBINVD/WBNOINVD are interruptible.
|
||||||
|
INVLPGB // NVLPGB and TLBSYNC instruction supported
|
||||||
|
LAHF // LAHF/SAHF in long mode
|
||||||
|
LAM // If set, CPU supports Linear Address Masking
|
||||||
|
LBRVIRT // LBR virtualization
|
||||||
LZCNT // LZCNT instruction
|
LZCNT // LZCNT instruction
|
||||||
|
MCAOVERFLOW // MCA overflow recovery support.
|
||||||
|
MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
|
||||||
|
MCOMMIT // MCOMMIT instruction supported
|
||||||
|
MD_CLEAR // VERW clears CPU buffers
|
||||||
MMX // standard MMX
|
MMX // standard MMX
|
||||||
MMXEXT // SSE integer functions or AMD MMX ext
|
MMXEXT // SSE integer functions or AMD MMX ext
|
||||||
|
MOVBE // MOVBE instruction (big-endian)
|
||||||
MOVDIR64B // Move 64 Bytes as Direct Store
|
MOVDIR64B // Move 64 Bytes as Direct Store
|
||||||
MOVDIRI // Move Doubleword as Direct Store
|
MOVDIRI // Move Doubleword as Direct Store
|
||||||
|
MOVSB_ZL // Fast Zero-Length MOVSB
|
||||||
|
MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
|
||||||
MPX // Intel MPX (Memory Protection Extensions)
|
MPX // Intel MPX (Memory Protection Extensions)
|
||||||
|
MSRIRC // Instruction Retired Counter MSR available
|
||||||
|
MSRLIST // Read/Write List of Model Specific Registers
|
||||||
|
MSR_PAGEFLUSH // Page Flush MSR available
|
||||||
|
NRIPS // Indicates support for NRIP save on VMEXIT
|
||||||
NX // NX (No-Execute) bit
|
NX // NX (No-Execute) bit
|
||||||
|
OSXSAVE // XSAVE enabled by OS
|
||||||
|
PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
|
||||||
POPCNT // POPCNT instruction
|
POPCNT // POPCNT instruction
|
||||||
|
PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
|
||||||
|
PREFETCHI // PREFETCHIT0/1 instructions
|
||||||
|
PSFD // Predictive Store Forward Disable
|
||||||
|
RDPRU // RDPRU instruction supported
|
||||||
RDRAND // RDRAND instruction is available
|
RDRAND // RDRAND instruction is available
|
||||||
RDSEED // RDSEED instruction is available
|
RDSEED // RDSEED instruction is available
|
||||||
RDTSCP // RDTSCP Instruction
|
RDTSCP // RDTSCP Instruction
|
||||||
|
RRSBA_CTRL // Restricted RSB Alternate
|
||||||
RTM // Restricted Transactional Memory
|
RTM // Restricted Transactional Memory
|
||||||
|
RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
|
||||||
SERIALIZE // Serialize Instruction Execution
|
SERIALIZE // Serialize Instruction Execution
|
||||||
|
SEV // AMD Secure Encrypted Virtualization supported
|
||||||
|
SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host
|
||||||
|
SEV_ALTERNATIVE // AMD SEV Alternate Injection supported
|
||||||
|
SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests
|
||||||
|
SEV_ES // AMD SEV Encrypted State supported
|
||||||
|
SEV_RESTRICTED // AMD SEV Restricted Injection supported
|
||||||
|
SEV_SNP // AMD SEV Secure Nested Paging supported
|
||||||
SGX // Software Guard Extensions
|
SGX // Software Guard Extensions
|
||||||
SGXLC // Software Guard Extensions Launch Control
|
SGXLC // Software Guard Extensions Launch Control
|
||||||
SHA // Intel SHA Extensions
|
SHA // Intel SHA Extensions
|
||||||
|
SME // AMD Secure Memory Encryption supported
|
||||||
|
SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
|
||||||
|
SPEC_CTRL_SSBD // Speculative Store Bypass Disable
|
||||||
|
SRBDS_CTRL // SRBDS mitigation MSR available
|
||||||
SSE // SSE functions
|
SSE // SSE functions
|
||||||
SSE2 // P4 SSE functions
|
SSE2 // P4 SSE functions
|
||||||
SSE3 // Prescott SSE3 functions
|
SSE3 // Prescott SSE3 functions
|
||||||
@ -140,14 +213,42 @@ const (
|
|||||||
SSE4A // AMD Barcelona microarchitecture SSE4a instructions
|
SSE4A // AMD Barcelona microarchitecture SSE4a instructions
|
||||||
SSSE3 // Conroe SSSE3 functions
|
SSSE3 // Conroe SSSE3 functions
|
||||||
STIBP // Single Thread Indirect Branch Predictors
|
STIBP // Single Thread Indirect Branch Predictors
|
||||||
|
STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
|
||||||
|
STOSB_SHORT // Fast short STOSB
|
||||||
|
SUCCOR // Software uncorrectable error containment and recovery capability.
|
||||||
|
SVM // AMD Secure Virtual Machine
|
||||||
|
SVMDA // Indicates support for the SVM decode assists.
|
||||||
|
SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control
|
||||||
|
SVML // AMD SVM lock. Indicates support for SVM-Lock.
|
||||||
|
SVMNP // AMD SVM nested paging
|
||||||
|
SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter
|
||||||
|
SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold
|
||||||
|
SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
|
||||||
|
SYSEE // SYSENTER and SYSEXIT instructions
|
||||||
TBM // AMD Trailing Bit Manipulation
|
TBM // AMD Trailing Bit Manipulation
|
||||||
|
TDX_GUEST // Intel Trust Domain Extensions Guest
|
||||||
|
TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
|
||||||
|
TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
|
||||||
|
TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||||
|
TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
|
||||||
TSXLDTRK // Intel TSX Suspend Load Address Tracking
|
TSXLDTRK // Intel TSX Suspend Load Address Tracking
|
||||||
VAES // Vector AES
|
VAES // Vector AES. AVX(512) versions requires additional checks.
|
||||||
|
VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits.
|
||||||
|
VMPL // AMD VM Permission Levels supported
|
||||||
|
VMSA_REGPROT // AMD VMSA Register Protection supported
|
||||||
VMX // Virtual Machine Extensions
|
VMX // Virtual Machine Extensions
|
||||||
VPCLMULQDQ // Carry-Less Multiplication Quadword
|
VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.
|
||||||
|
VTE // AMD Virtual Transparent Encryption supported
|
||||||
WAITPKG // TPAUSE, UMONITOR, UMWAIT
|
WAITPKG // TPAUSE, UMONITOR, UMWAIT
|
||||||
WBNOINVD // Write Back and Do Not Invalidate Cache
|
WBNOINVD // Write Back and Do Not Invalidate Cache
|
||||||
|
WRMSRNS // Non-Serializing Write to Model Specific Register
|
||||||
|
X87 // FPU
|
||||||
|
XGETBV1 // Supports XGETBV with ECX = 1
|
||||||
XOP // Bulldozer XOP functions
|
XOP // Bulldozer XOP functions
|
||||||
|
XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV
|
||||||
|
XSAVEC // Supports XSAVEC and the compacted form of XRSTOR.
|
||||||
|
XSAVEOPT // XSAVEOPT available
|
||||||
|
XSAVES // Supports XSAVES/XRSTORS and IA32_XSS
|
||||||
|
|
||||||
// ARM features:
|
// ARM features:
|
||||||
AESARM // AES instructions
|
AESARM // AES instructions
|
||||||
@ -174,7 +275,6 @@ const (
|
|||||||
SM3 // SM3 instructions
|
SM3 // SM3 instructions
|
||||||
SM4 // SM4 instructions
|
SM4 // SM4 instructions
|
||||||
SVE // Scalable Vector Extension
|
SVE // Scalable Vector Extension
|
||||||
|
|
||||||
// Keep it last. It automatically defines the size of []flagSet
|
// Keep it last. It automatically defines the size of []flagSet
|
||||||
lastID
|
lastID
|
||||||
|
|
||||||
@ -192,8 +292,10 @@ type CPUInfo struct {
|
|||||||
LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
|
LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
|
||||||
Family int // CPU family number
|
Family int // CPU family number
|
||||||
Model int // CPU model number
|
Model int // CPU model number
|
||||||
|
Stepping int // CPU stepping info
|
||||||
CacheLine int // Cache line size in bytes. Will be 0 if undetectable.
|
CacheLine int // Cache line size in bytes. Will be 0 if undetectable.
|
||||||
Hz int64 // Clock speed, if known, 0 otherwise
|
Hz int64 // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed.
|
||||||
|
BoostFreq int64 // Max clock speed, if known, 0 otherwise
|
||||||
Cache struct {
|
Cache struct {
|
||||||
L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
|
L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
|
||||||
L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected
|
L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected
|
||||||
@ -209,6 +311,7 @@ var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
|
|||||||
var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32)
|
var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32)
|
||||||
var xgetbv func(index uint32) (eax, edx uint32)
|
var xgetbv func(index uint32) (eax, edx uint32)
|
||||||
var rdtscpAsm func() (eax, ebx, ecx, edx uint32)
|
var rdtscpAsm func() (eax, ebx, ecx, edx uint32)
|
||||||
|
var darwinHasAVX512 = func() bool { return false }
|
||||||
|
|
||||||
// CPU contains information about the CPU as detected on startup,
|
// CPU contains information about the CPU as detected on startup,
|
||||||
// or when Detect last was called.
|
// or when Detect last was called.
|
||||||
@ -292,10 +395,66 @@ func (c CPUInfo) Supports(ids ...FeatureID) bool {
|
|||||||
|
|
||||||
// Has allows for checking a single feature.
|
// Has allows for checking a single feature.
|
||||||
// Should be inlined by the compiler.
|
// Should be inlined by the compiler.
|
||||||
func (c CPUInfo) Has(id FeatureID) bool {
|
func (c *CPUInfo) Has(id FeatureID) bool {
|
||||||
return c.featureSet.inSet(id)
|
return c.featureSet.inSet(id)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// AnyOf returns whether the CPU supports one or more of the requested features.
|
||||||
|
func (c CPUInfo) AnyOf(ids ...FeatureID) bool {
|
||||||
|
for _, id := range ids {
|
||||||
|
if c.featureSet.inSet(id) {
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return false
|
||||||
|
}
|
||||||
|
|
||||||
|
// Features contains several features combined for a fast check using
|
||||||
|
// CpuInfo.HasAll
|
||||||
|
type Features *flagSet
|
||||||
|
|
||||||
|
// CombineFeatures allows to combine several features for a close to constant time lookup.
|
||||||
|
func CombineFeatures(ids ...FeatureID) Features {
|
||||||
|
var v flagSet
|
||||||
|
for _, id := range ids {
|
||||||
|
v.set(id)
|
||||||
|
}
|
||||||
|
return &v
|
||||||
|
}
|
||||||
|
|
||||||
|
func (c *CPUInfo) HasAll(f Features) bool {
|
||||||
|
return c.featureSet.hasSetP(f)
|
||||||
|
}
|
||||||
|
|
||||||
|
// https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
|
||||||
|
var oneOfLevel = CombineFeatures(SYSEE, SYSCALL)
|
||||||
|
var level1Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2)
|
||||||
|
var level2Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3)
|
||||||
|
var level3Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE)
|
||||||
|
var level4Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL)
|
||||||
|
|
||||||
|
// X64Level returns the microarchitecture level detected on the CPU.
|
||||||
|
// If features are lacking or non x64 mode, 0 is returned.
|
||||||
|
// See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
|
||||||
|
func (c CPUInfo) X64Level() int {
|
||||||
|
if !c.featureSet.hasOneOf(oneOfLevel) {
|
||||||
|
return 0
|
||||||
|
}
|
||||||
|
if c.featureSet.hasSetP(level4Features) {
|
||||||
|
return 4
|
||||||
|
}
|
||||||
|
if c.featureSet.hasSetP(level3Features) {
|
||||||
|
return 3
|
||||||
|
}
|
||||||
|
if c.featureSet.hasSetP(level2Features) {
|
||||||
|
return 2
|
||||||
|
}
|
||||||
|
if c.featureSet.hasSetP(level1Features) {
|
||||||
|
return 1
|
||||||
|
}
|
||||||
|
return 0
|
||||||
|
}
|
||||||
|
|
||||||
// Disable will disable one or several features.
|
// Disable will disable one or several features.
|
||||||
func (c *CPUInfo) Disable(ids ...FeatureID) bool {
|
func (c *CPUInfo) Disable(ids ...FeatureID) bool {
|
||||||
for _, id := range ids {
|
for _, id := range ids {
|
||||||
@ -318,11 +477,10 @@ func (c CPUInfo) IsVendor(v Vendor) bool {
|
|||||||
return c.VendorID == v
|
return c.VendorID == v
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// FeatureSet returns all available features as strings.
|
||||||
func (c CPUInfo) FeatureSet() []string {
|
func (c CPUInfo) FeatureSet() []string {
|
||||||
s := make([]string, 0)
|
s := make([]string, 0, c.featureSet.nEnabled())
|
||||||
for _, f := range c.featureSet.Strings() {
|
s = append(s, c.featureSet.Strings()...)
|
||||||
s = append(s, f)
|
|
||||||
}
|
|
||||||
return s
|
return s
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -361,25 +519,42 @@ func (c CPUInfo) LogicalCPU() int {
|
|||||||
return int(ebx >> 24)
|
return int(ebx >> 24)
|
||||||
}
|
}
|
||||||
|
|
||||||
// hertz tries to compute the clock speed of the CPU. If leaf 15 is
|
// frequencies tries to compute the clock speed of the CPU. If leaf 15 is
|
||||||
// supported, use it, otherwise parse the brand string. Yes, really.
|
// supported, use it, otherwise parse the brand string. Yes, really.
|
||||||
func hertz(model string) int64 {
|
func (c *CPUInfo) frequencies() {
|
||||||
|
c.Hz, c.BoostFreq = 0, 0
|
||||||
mfi := maxFunctionID()
|
mfi := maxFunctionID()
|
||||||
if mfi >= 0x15 {
|
if mfi >= 0x15 {
|
||||||
eax, ebx, ecx, _ := cpuid(0x15)
|
eax, ebx, ecx, _ := cpuid(0x15)
|
||||||
if eax != 0 && ebx != 0 && ecx != 0 {
|
if eax != 0 && ebx != 0 && ecx != 0 {
|
||||||
return int64((int64(ecx) * int64(ebx)) / int64(eax))
|
c.Hz = (int64(ecx) * int64(ebx)) / int64(eax)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
if mfi >= 0x16 {
|
||||||
|
a, b, _, _ := cpuid(0x16)
|
||||||
|
// Base...
|
||||||
|
if a&0xffff > 0 {
|
||||||
|
c.Hz = int64(a&0xffff) * 1_000_000
|
||||||
|
}
|
||||||
|
// Boost...
|
||||||
|
if b&0xffff > 0 {
|
||||||
|
c.BoostFreq = int64(b&0xffff) * 1_000_000
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if c.Hz > 0 {
|
||||||
|
return
|
||||||
|
}
|
||||||
|
|
||||||
// computeHz determines the official rated speed of a CPU from its brand
|
// computeHz determines the official rated speed of a CPU from its brand
|
||||||
// string. This insanity is *actually the official documented way to do
|
// string. This insanity is *actually the official documented way to do
|
||||||
// this according to Intel*, prior to leaf 0x15 existing. The official
|
// this according to Intel*, prior to leaf 0x15 existing. The official
|
||||||
// documentation only shows this working for exactly `x.xx` or `xxxx`
|
// documentation only shows this working for exactly `x.xx` or `xxxx`
|
||||||
// cases, e.g., `2.50GHz` or `1300MHz`; this parser will accept other
|
// cases, e.g., `2.50GHz` or `1300MHz`; this parser will accept other
|
||||||
// sizes.
|
// sizes.
|
||||||
|
model := c.BrandName
|
||||||
hz := strings.LastIndex(model, "Hz")
|
hz := strings.LastIndex(model, "Hz")
|
||||||
if hz < 3 {
|
if hz < 3 {
|
||||||
return 0
|
return
|
||||||
}
|
}
|
||||||
var multiplier int64
|
var multiplier int64
|
||||||
switch model[hz-1] {
|
switch model[hz-1] {
|
||||||
@ -391,7 +566,7 @@ func hertz(model string) int64 {
|
|||||||
multiplier = 1000 * 1000 * 1000 * 1000
|
multiplier = 1000 * 1000 * 1000 * 1000
|
||||||
}
|
}
|
||||||
if multiplier == 0 {
|
if multiplier == 0 {
|
||||||
return 0
|
return
|
||||||
}
|
}
|
||||||
freq := int64(0)
|
freq := int64(0)
|
||||||
divisor := int64(0)
|
divisor := int64(0)
|
||||||
@ -403,21 +578,22 @@ func hertz(model string) int64 {
|
|||||||
decimalShift *= 10
|
decimalShift *= 10
|
||||||
} else if model[i] == '.' {
|
} else if model[i] == '.' {
|
||||||
if divisor != 0 {
|
if divisor != 0 {
|
||||||
return 0
|
return
|
||||||
}
|
}
|
||||||
divisor = decimalShift
|
divisor = decimalShift
|
||||||
} else {
|
} else {
|
||||||
return 0
|
return
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
// we didn't find a space
|
// we didn't find a space
|
||||||
if i < 0 {
|
if i < 0 {
|
||||||
return 0
|
return
|
||||||
}
|
}
|
||||||
if divisor != 0 {
|
if divisor != 0 {
|
||||||
return (freq * multiplier) / divisor
|
c.Hz = (freq * multiplier) / divisor
|
||||||
|
return
|
||||||
}
|
}
|
||||||
return freq * multiplier
|
c.Hz = freq * multiplier
|
||||||
}
|
}
|
||||||
|
|
||||||
// VM Will return true if the cpu id indicates we are in
|
// VM Will return true if the cpu id indicates we are in
|
||||||
@ -437,7 +613,7 @@ const flagMask = flagBits - 1
|
|||||||
// flagSet contains detected cpu features and characteristics in an array of flags
|
// flagSet contains detected cpu features and characteristics in an array of flags
|
||||||
type flagSet [(lastID + flagMask) / flagBits]flags
|
type flagSet [(lastID + flagMask) / flagBits]flags
|
||||||
|
|
||||||
func (s flagSet) inSet(feat FeatureID) bool {
|
func (s *flagSet) inSet(feat FeatureID) bool {
|
||||||
return s[feat>>flagBitsLog2]&(1<<(feat&flagMask)) != 0
|
return s[feat>>flagBitsLog2]&(1<<(feat&flagMask)) != 0
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -466,6 +642,52 @@ func (s *flagSet) or(other flagSet) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// hasSet returns whether all features are present.
|
||||||
|
func (s *flagSet) hasSet(other flagSet) bool {
|
||||||
|
for i, v := range other[:] {
|
||||||
|
if s[i]&v != v {
|
||||||
|
return false
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
// hasSet returns whether all features are present.
|
||||||
|
func (s *flagSet) hasSetP(other *flagSet) bool {
|
||||||
|
for i, v := range other[:] {
|
||||||
|
if s[i]&v != v {
|
||||||
|
return false
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
// hasOneOf returns whether one or more features are present.
|
||||||
|
func (s *flagSet) hasOneOf(other *flagSet) bool {
|
||||||
|
for i, v := range other[:] {
|
||||||
|
if s[i]&v != 0 {
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return false
|
||||||
|
}
|
||||||
|
|
||||||
|
// nEnabled will return the number of enabled flags.
|
||||||
|
func (s *flagSet) nEnabled() (n int) {
|
||||||
|
for _, v := range s[:] {
|
||||||
|
n += bits.OnesCount64(uint64(v))
|
||||||
|
}
|
||||||
|
return n
|
||||||
|
}
|
||||||
|
|
||||||
|
func flagSetWith(feat ...FeatureID) flagSet {
|
||||||
|
var res flagSet
|
||||||
|
for _, f := range feat {
|
||||||
|
res.set(f)
|
||||||
|
}
|
||||||
|
return res
|
||||||
|
}
|
||||||
|
|
||||||
// ParseFeature will parse the string and return the ID of the matching feature.
|
// ParseFeature will parse the string and return the ID of the matching feature.
|
||||||
// Will return UNKNOWN if not found.
|
// Will return UNKNOWN if not found.
|
||||||
func ParseFeature(s string) FeatureID {
|
func ParseFeature(s string) FeatureID {
|
||||||
@ -546,7 +768,7 @@ func threadsPerCore() int {
|
|||||||
if vend == AMD {
|
if vend == AMD {
|
||||||
// Workaround for AMD returning 0, assume 2 if >= Zen 2
|
// Workaround for AMD returning 0, assume 2 if >= Zen 2
|
||||||
// It will be more correct than not.
|
// It will be more correct than not.
|
||||||
fam, _ := familyModel()
|
fam, _, _ := familyModel()
|
||||||
_, _, _, d := cpuid(1)
|
_, _, _, d := cpuid(1)
|
||||||
if (d&(1<<28)) != 0 && fam >= 23 {
|
if (d&(1<<28)) != 0 && fam >= 23 {
|
||||||
return 2
|
return 2
|
||||||
@ -584,14 +806,27 @@ func logicalCores() int {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
func familyModel() (int, int) {
|
func familyModel() (family, model, stepping int) {
|
||||||
if maxFunctionID() < 0x1 {
|
if maxFunctionID() < 0x1 {
|
||||||
return 0, 0
|
return 0, 0, 0
|
||||||
}
|
}
|
||||||
eax, _, _, _ := cpuid(1)
|
eax, _, _, _ := cpuid(1)
|
||||||
family := ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff)
|
// If BaseFamily[3:0] is less than Fh then ExtendedFamily[7:0] is reserved and Family is equal to BaseFamily[3:0].
|
||||||
model := ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0)
|
family = int((eax >> 8) & 0xf)
|
||||||
return int(family), int(model)
|
extFam := family == 0x6 // Intel is 0x6, needs extended model.
|
||||||
|
if family == 0xf {
|
||||||
|
// Add ExtFamily
|
||||||
|
family += int((eax >> 20) & 0xff)
|
||||||
|
extFam = true
|
||||||
|
}
|
||||||
|
// If BaseFamily[3:0] is less than 0Fh then ExtendedModel[3:0] is reserved and Model is equal to BaseModel[3:0].
|
||||||
|
model = int((eax >> 4) & 0xf)
|
||||||
|
if extFam {
|
||||||
|
// Add ExtModel
|
||||||
|
model += int((eax >> 12) & 0xf0)
|
||||||
|
}
|
||||||
|
stepping = int(eax & 0xf)
|
||||||
|
return family, model, stepping
|
||||||
}
|
}
|
||||||
|
|
||||||
func physicalCores() int {
|
func physicalCores() int {
|
||||||
@ -675,6 +910,7 @@ func (c *CPUInfo) cacheSize() {
|
|||||||
if maxFunctionID() < 4 {
|
if maxFunctionID() < 4 {
|
||||||
return
|
return
|
||||||
}
|
}
|
||||||
|
c.Cache.L1I, c.Cache.L1D, c.Cache.L2, c.Cache.L3 = 0, 0, 0, 0
|
||||||
for i := uint32(0); ; i++ {
|
for i := uint32(0); ; i++ {
|
||||||
eax, ebx, ecx, _ := cpuidex(4, i)
|
eax, ebx, ecx, _ := cpuidex(4, i)
|
||||||
cacheType := eax & 15
|
cacheType := eax & 15
|
||||||
@ -725,9 +961,14 @@ func (c *CPUInfo) cacheSize() {
|
|||||||
c.Cache.L2 = int(((ecx >> 16) & 0xFFFF) * 1024)
|
c.Cache.L2 = int(((ecx >> 16) & 0xFFFF) * 1024)
|
||||||
|
|
||||||
// CPUID Fn8000_001D_EAX_x[N:0] Cache Properties
|
// CPUID Fn8000_001D_EAX_x[N:0] Cache Properties
|
||||||
if maxExtendedFunction() < 0x8000001D {
|
if maxExtendedFunction() < 0x8000001D || !c.Has(TOPEXT) {
|
||||||
return
|
return
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Xen Hypervisor is buggy and returns the same entry no matter ECX value.
|
||||||
|
// Hack: When we encounter the same entry 100 times we break.
|
||||||
|
nSame := 0
|
||||||
|
var last uint32
|
||||||
for i := uint32(0); i < math.MaxUint32; i++ {
|
for i := uint32(0); i < math.MaxUint32; i++ {
|
||||||
eax, ebx, ecx, _ := cpuidex(0x8000001D, i)
|
eax, ebx, ecx, _ := cpuidex(0x8000001D, i)
|
||||||
|
|
||||||
@ -743,6 +984,16 @@ func (c *CPUInfo) cacheSize() {
|
|||||||
return
|
return
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Check for the same value repeated.
|
||||||
|
comb := eax ^ ebx ^ ecx
|
||||||
|
if comb == last {
|
||||||
|
nSame++
|
||||||
|
if nSame == 100 {
|
||||||
|
return
|
||||||
|
}
|
||||||
|
}
|
||||||
|
last = comb
|
||||||
|
|
||||||
switch level {
|
switch level {
|
||||||
case 1:
|
case 1:
|
||||||
switch typ {
|
switch typ {
|
||||||
@ -767,8 +1018,6 @@ func (c *CPUInfo) cacheSize() {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return
|
|
||||||
}
|
}
|
||||||
|
|
||||||
type SGXEPCSection struct {
|
type SGXEPCSection struct {
|
||||||
@ -829,21 +1078,26 @@ func support() flagSet {
|
|||||||
if mfi < 0x1 {
|
if mfi < 0x1 {
|
||||||
return fs
|
return fs
|
||||||
}
|
}
|
||||||
family, model := familyModel()
|
family, model, _ := familyModel()
|
||||||
|
|
||||||
_, _, c, d := cpuid(1)
|
_, _, c, d := cpuid(1)
|
||||||
|
fs.setIf((d&(1<<0)) != 0, X87)
|
||||||
|
fs.setIf((d&(1<<8)) != 0, CMPXCHG8)
|
||||||
|
fs.setIf((d&(1<<11)) != 0, SYSEE)
|
||||||
fs.setIf((d&(1<<15)) != 0, CMOV)
|
fs.setIf((d&(1<<15)) != 0, CMOV)
|
||||||
fs.setIf((d&(1<<23)) != 0, MMX)
|
fs.setIf((d&(1<<23)) != 0, MMX)
|
||||||
fs.setIf((d&(1<<25)) != 0, MMXEXT)
|
fs.setIf((d&(1<<24)) != 0, FXSR)
|
||||||
|
fs.setIf((d&(1<<25)) != 0, FXSROPT)
|
||||||
fs.setIf((d&(1<<25)) != 0, SSE)
|
fs.setIf((d&(1<<25)) != 0, SSE)
|
||||||
fs.setIf((d&(1<<26)) != 0, SSE2)
|
fs.setIf((d&(1<<26)) != 0, SSE2)
|
||||||
fs.setIf((c&1) != 0, SSE3)
|
fs.setIf((c&1) != 0, SSE3)
|
||||||
fs.setIf((c&(1<<5)) != 0, VMX)
|
fs.setIf((c&(1<<5)) != 0, VMX)
|
||||||
fs.setIf((c&0x00000200) != 0, SSSE3)
|
fs.setIf((c&(1<<9)) != 0, SSSE3)
|
||||||
fs.setIf((c&0x00080000) != 0, SSE4)
|
fs.setIf((c&(1<<19)) != 0, SSE4)
|
||||||
fs.setIf((c&0x00100000) != 0, SSE42)
|
fs.setIf((c&(1<<20)) != 0, SSE42)
|
||||||
fs.setIf((c&(1<<25)) != 0, AESNI)
|
fs.setIf((c&(1<<25)) != 0, AESNI)
|
||||||
fs.setIf((c&(1<<1)) != 0, CLMUL)
|
fs.setIf((c&(1<<1)) != 0, CLMUL)
|
||||||
|
fs.setIf(c&(1<<22) != 0, MOVBE)
|
||||||
fs.setIf(c&(1<<23) != 0, POPCNT)
|
fs.setIf(c&(1<<23) != 0, POPCNT)
|
||||||
fs.setIf(c&(1<<30) != 0, RDRAND)
|
fs.setIf(c&(1<<30) != 0, RDRAND)
|
||||||
|
|
||||||
@ -859,6 +1113,8 @@ func support() flagSet {
|
|||||||
if vend == AMD && (d&(1<<28)) != 0 && mfi >= 4 {
|
if vend == AMD && (d&(1<<28)) != 0 && mfi >= 4 {
|
||||||
fs.setIf(threadsPerCore() > 1, HTT)
|
fs.setIf(threadsPerCore() > 1, HTT)
|
||||||
}
|
}
|
||||||
|
fs.setIf(c&1<<26 != 0, XSAVE)
|
||||||
|
fs.setIf(c&1<<27 != 0, OSXSAVE)
|
||||||
// Check XGETBV/XSAVE (26), OXSAVE (27) and AVX (28) bits
|
// Check XGETBV/XSAVE (26), OXSAVE (27) and AVX (28) bits
|
||||||
const avxCheck = 1<<26 | 1<<27 | 1<<28
|
const avxCheck = 1<<26 | 1<<27 | 1<<28
|
||||||
if c&avxCheck == avxCheck {
|
if c&avxCheck == avxCheck {
|
||||||
@ -884,7 +1140,6 @@ func support() flagSet {
|
|||||||
// Check AVX2, AVX2 requires OS support, but BMI1/2 don't.
|
// Check AVX2, AVX2 requires OS support, but BMI1/2 don't.
|
||||||
if mfi >= 7 {
|
if mfi >= 7 {
|
||||||
_, ebx, ecx, edx := cpuidex(7, 0)
|
_, ebx, ecx, edx := cpuidex(7, 0)
|
||||||
eax1, _, _, _ := cpuidex(7, 1)
|
|
||||||
if fs.inSet(AVX) && (ebx&0x00000020) != 0 {
|
if fs.inSet(AVX) && (ebx&0x00000020) != 0 {
|
||||||
fs.set(AVX2)
|
fs.set(AVX2)
|
||||||
}
|
}
|
||||||
@ -901,18 +1156,52 @@ func support() flagSet {
|
|||||||
fs.setIf(ebx&(1<<18) != 0, RDSEED)
|
fs.setIf(ebx&(1<<18) != 0, RDSEED)
|
||||||
fs.setIf(ebx&(1<<19) != 0, ADX)
|
fs.setIf(ebx&(1<<19) != 0, ADX)
|
||||||
fs.setIf(ebx&(1<<29) != 0, SHA)
|
fs.setIf(ebx&(1<<29) != 0, SHA)
|
||||||
|
|
||||||
// CPUID.(EAX=7, ECX=0).ECX
|
// CPUID.(EAX=7, ECX=0).ECX
|
||||||
fs.setIf(ecx&(1<<5) != 0, WAITPKG)
|
fs.setIf(ecx&(1<<5) != 0, WAITPKG)
|
||||||
|
fs.setIf(ecx&(1<<7) != 0, CETSS)
|
||||||
|
fs.setIf(ecx&(1<<8) != 0, GFNI)
|
||||||
|
fs.setIf(ecx&(1<<9) != 0, VAES)
|
||||||
|
fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ)
|
||||||
|
fs.setIf(ecx&(1<<13) != 0, TME)
|
||||||
fs.setIf(ecx&(1<<25) != 0, CLDEMOTE)
|
fs.setIf(ecx&(1<<25) != 0, CLDEMOTE)
|
||||||
fs.setIf(ecx&(1<<27) != 0, MOVDIRI)
|
fs.setIf(ecx&(1<<27) != 0, MOVDIRI)
|
||||||
fs.setIf(ecx&(1<<28) != 0, MOVDIR64B)
|
fs.setIf(ecx&(1<<28) != 0, MOVDIR64B)
|
||||||
fs.setIf(ecx&(1<<29) != 0, ENQCMD)
|
fs.setIf(ecx&(1<<29) != 0, ENQCMD)
|
||||||
fs.setIf(ecx&(1<<30) != 0, SGXLC)
|
fs.setIf(ecx&(1<<30) != 0, SGXLC)
|
||||||
|
|
||||||
// CPUID.(EAX=7, ECX=0).EDX
|
// CPUID.(EAX=7, ECX=0).EDX
|
||||||
|
fs.setIf(edx&(1<<4) != 0, FSRM)
|
||||||
|
fs.setIf(edx&(1<<9) != 0, SRBDS_CTRL)
|
||||||
|
fs.setIf(edx&(1<<10) != 0, MD_CLEAR)
|
||||||
|
fs.setIf(edx&(1<<11) != 0, RTM_ALWAYS_ABORT)
|
||||||
fs.setIf(edx&(1<<14) != 0, SERIALIZE)
|
fs.setIf(edx&(1<<14) != 0, SERIALIZE)
|
||||||
|
fs.setIf(edx&(1<<15) != 0, HYBRID_CPU)
|
||||||
fs.setIf(edx&(1<<16) != 0, TSXLDTRK)
|
fs.setIf(edx&(1<<16) != 0, TSXLDTRK)
|
||||||
|
fs.setIf(edx&(1<<18) != 0, PCONFIG)
|
||||||
|
fs.setIf(edx&(1<<20) != 0, CETIBT)
|
||||||
fs.setIf(edx&(1<<26) != 0, IBPB)
|
fs.setIf(edx&(1<<26) != 0, IBPB)
|
||||||
fs.setIf(edx&(1<<27) != 0, STIBP)
|
fs.setIf(edx&(1<<27) != 0, STIBP)
|
||||||
|
fs.setIf(edx&(1<<28) != 0, FLUSH_L1D)
|
||||||
|
fs.setIf(edx&(1<<29) != 0, IA32_ARCH_CAP)
|
||||||
|
fs.setIf(edx&(1<<30) != 0, IA32_CORE_CAP)
|
||||||
|
fs.setIf(edx&(1<<31) != 0, SPEC_CTRL_SSBD)
|
||||||
|
|
||||||
|
// CPUID.(EAX=7, ECX=1).EAX
|
||||||
|
eax1, _, _, edx1 := cpuidex(7, 1)
|
||||||
|
fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
|
||||||
|
fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
|
||||||
|
fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
|
||||||
|
fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT)
|
||||||
|
fs.setIf(eax1&(1<<12) != 0, CMPSB_SCADBS_SHORT)
|
||||||
|
fs.setIf(eax1&(1<<22) != 0, HRESET)
|
||||||
|
fs.setIf(eax1&(1<<23) != 0, AVXIFMA)
|
||||||
|
fs.setIf(eax1&(1<<26) != 0, LAM)
|
||||||
|
|
||||||
|
// CPUID.(EAX=7, ECX=1).EDX
|
||||||
|
fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8)
|
||||||
|
fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT)
|
||||||
|
fs.setIf(edx1&(1<<14) != 0, PREFETCHI)
|
||||||
|
|
||||||
// Only detect AVX-512 features if XGETBV is supported
|
// Only detect AVX-512 features if XGETBV is supported
|
||||||
if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
|
if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
|
||||||
@ -922,7 +1211,11 @@ func support() flagSet {
|
|||||||
// Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
|
// Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
|
||||||
// ZMM16-ZMM31 state are enabled by OS)
|
// ZMM16-ZMM31 state are enabled by OS)
|
||||||
/// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
|
/// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
|
||||||
if (eax>>5)&7 == 7 && (eax>>1)&3 == 3 {
|
hasAVX512 := (eax>>5)&7 == 7 && (eax>>1)&3 == 3
|
||||||
|
if runtime.GOOS == "darwin" {
|
||||||
|
hasAVX512 = fs.inSet(AVX) && darwinHasAVX512()
|
||||||
|
}
|
||||||
|
if hasAVX512 {
|
||||||
fs.setIf(ebx&(1<<16) != 0, AVX512F)
|
fs.setIf(ebx&(1<<16) != 0, AVX512F)
|
||||||
fs.setIf(ebx&(1<<17) != 0, AVX512DQ)
|
fs.setIf(ebx&(1<<17) != 0, AVX512DQ)
|
||||||
fs.setIf(ebx&(1<<21) != 0, AVX512IFMA)
|
fs.setIf(ebx&(1<<21) != 0, AVX512IFMA)
|
||||||
@ -934,49 +1227,137 @@ func support() flagSet {
|
|||||||
// ecx
|
// ecx
|
||||||
fs.setIf(ecx&(1<<1) != 0, AVX512VBMI)
|
fs.setIf(ecx&(1<<1) != 0, AVX512VBMI)
|
||||||
fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2)
|
fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2)
|
||||||
fs.setIf(ecx&(1<<8) != 0, GFNI)
|
|
||||||
fs.setIf(ecx&(1<<9) != 0, VAES)
|
|
||||||
fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ)
|
|
||||||
fs.setIf(ecx&(1<<11) != 0, AVX512VNNI)
|
fs.setIf(ecx&(1<<11) != 0, AVX512VNNI)
|
||||||
fs.setIf(ecx&(1<<12) != 0, AVX512BITALG)
|
fs.setIf(ecx&(1<<12) != 0, AVX512BITALG)
|
||||||
fs.setIf(ecx&(1<<14) != 0, AVX512VPOPCNTDQ)
|
fs.setIf(ecx&(1<<14) != 0, AVX512VPOPCNTDQ)
|
||||||
// edx
|
// edx
|
||||||
fs.setIf(edx&(1<<8) != 0, AVX512VP2INTERSECT)
|
fs.setIf(edx&(1<<8) != 0, AVX512VP2INTERSECT)
|
||||||
fs.setIf(edx&(1<<22) != 0, AMXBF16)
|
fs.setIf(edx&(1<<22) != 0, AMXBF16)
|
||||||
|
fs.setIf(edx&(1<<23) != 0, AVX512FP16)
|
||||||
fs.setIf(edx&(1<<24) != 0, AMXTILE)
|
fs.setIf(edx&(1<<24) != 0, AMXTILE)
|
||||||
fs.setIf(edx&(1<<25) != 0, AMXINT8)
|
fs.setIf(edx&(1<<25) != 0, AMXINT8)
|
||||||
// eax1 = CPUID.(EAX=7, ECX=1).EAX
|
// eax1 = CPUID.(EAX=7, ECX=1).EAX
|
||||||
fs.setIf(eax1&(1<<5) != 0, AVX512BF16)
|
fs.setIf(eax1&(1<<5) != 0, AVX512BF16)
|
||||||
|
fs.setIf(eax1&(1<<19) != 0, WRMSRNS)
|
||||||
|
fs.setIf(eax1&(1<<21) != 0, AMXFP16)
|
||||||
|
fs.setIf(eax1&(1<<27) != 0, MSRLIST)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// CPUID.(EAX=7, ECX=2)
|
||||||
|
_, _, _, edx = cpuidex(7, 2)
|
||||||
|
fs.setIf(edx&(1<<0) != 0, PSFD)
|
||||||
|
fs.setIf(edx&(1<<1) != 0, IDPRED_CTRL)
|
||||||
|
fs.setIf(edx&(1<<2) != 0, RRSBA_CTRL)
|
||||||
|
fs.setIf(edx&(1<<4) != 0, BHI_CTRL)
|
||||||
|
fs.setIf(edx&(1<<5) != 0, MCDT_NO)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
|
||||||
|
// EAX
|
||||||
|
// Bit 00: XSAVEOPT is available.
|
||||||
|
// Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
|
||||||
|
// Bit 02: Supports XGETBV with ECX = 1 if set.
|
||||||
|
// Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
|
||||||
|
// Bits 31 - 04: Reserved.
|
||||||
|
// EBX
|
||||||
|
// Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
|
||||||
|
// ECX
|
||||||
|
// Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] is 1.
|
||||||
|
// EDX?
|
||||||
|
// Bits 07 - 00: Used for XCR0. Bit 08: PT state. Bit 09: Used for XCR0. Bits 12 - 10: Reserved. Bit 13: HWP state. Bits 31 - 14: Reserved.
|
||||||
|
if mfi >= 0xd {
|
||||||
|
if fs.inSet(XSAVE) {
|
||||||
|
eax, _, _, _ := cpuidex(0xd, 1)
|
||||||
|
fs.setIf(eax&(1<<0) != 0, XSAVEOPT)
|
||||||
|
fs.setIf(eax&(1<<1) != 0, XSAVEC)
|
||||||
|
fs.setIf(eax&(1<<2) != 0, XGETBV1)
|
||||||
|
fs.setIf(eax&(1<<3) != 0, XSAVES)
|
||||||
|
}
|
||||||
|
}
|
||||||
if maxExtendedFunction() >= 0x80000001 {
|
if maxExtendedFunction() >= 0x80000001 {
|
||||||
_, _, c, d := cpuid(0x80000001)
|
_, _, c, d := cpuid(0x80000001)
|
||||||
if (c & (1 << 5)) != 0 {
|
if (c & (1 << 5)) != 0 {
|
||||||
fs.set(LZCNT)
|
fs.set(LZCNT)
|
||||||
fs.set(POPCNT)
|
fs.set(POPCNT)
|
||||||
}
|
}
|
||||||
fs.setIf((c&(1<<10)) != 0, IBS)
|
// ECX
|
||||||
fs.setIf((d&(1<<31)) != 0, AMD3DNOW)
|
fs.setIf((c&(1<<0)) != 0, LAHF)
|
||||||
fs.setIf((d&(1<<30)) != 0, AMD3DNOWEXT)
|
fs.setIf((c&(1<<2)) != 0, SVM)
|
||||||
fs.setIf((d&(1<<23)) != 0, MMX)
|
|
||||||
fs.setIf((d&(1<<22)) != 0, MMXEXT)
|
|
||||||
fs.setIf((c&(1<<6)) != 0, SSE4A)
|
fs.setIf((c&(1<<6)) != 0, SSE4A)
|
||||||
|
fs.setIf((c&(1<<10)) != 0, IBS)
|
||||||
|
fs.setIf((c&(1<<22)) != 0, TOPEXT)
|
||||||
|
|
||||||
|
// EDX
|
||||||
|
fs.setIf(d&(1<<11) != 0, SYSCALL)
|
||||||
fs.setIf(d&(1<<20) != 0, NX)
|
fs.setIf(d&(1<<20) != 0, NX)
|
||||||
|
fs.setIf(d&(1<<22) != 0, MMXEXT)
|
||||||
|
fs.setIf(d&(1<<23) != 0, MMX)
|
||||||
|
fs.setIf(d&(1<<24) != 0, FXSR)
|
||||||
|
fs.setIf(d&(1<<25) != 0, FXSROPT)
|
||||||
fs.setIf(d&(1<<27) != 0, RDTSCP)
|
fs.setIf(d&(1<<27) != 0, RDTSCP)
|
||||||
|
fs.setIf(d&(1<<30) != 0, AMD3DNOWEXT)
|
||||||
|
fs.setIf(d&(1<<31) != 0, AMD3DNOW)
|
||||||
|
|
||||||
/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
|
/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
|
||||||
* used unless the OS has AVX support. */
|
* used unless the OS has AVX support. */
|
||||||
if fs.inSet(AVX) {
|
if fs.inSet(AVX) {
|
||||||
fs.setIf((c&0x00000800) != 0, XOP)
|
fs.setIf((c&(1<<11)) != 0, XOP)
|
||||||
fs.setIf((c&0x00010000) != 0, FMA4)
|
fs.setIf((c&(1<<16)) != 0, FMA4)
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
if maxExtendedFunction() >= 0x80000007 {
|
||||||
|
_, b, _, d := cpuid(0x80000007)
|
||||||
|
fs.setIf((b&(1<<0)) != 0, MCAOVERFLOW)
|
||||||
|
fs.setIf((b&(1<<1)) != 0, SUCCOR)
|
||||||
|
fs.setIf((b&(1<<2)) != 0, HWA)
|
||||||
|
fs.setIf((d&(1<<9)) != 0, CPBOOST)
|
||||||
|
}
|
||||||
|
|
||||||
if maxExtendedFunction() >= 0x80000008 {
|
if maxExtendedFunction() >= 0x80000008 {
|
||||||
_, b, _, _ := cpuid(0x80000008)
|
_, b, _, _ := cpuid(0x80000008)
|
||||||
|
fs.setIf(b&(1<<28) != 0, PSFD)
|
||||||
|
fs.setIf(b&(1<<27) != 0, CPPC)
|
||||||
|
fs.setIf(b&(1<<24) != 0, SPEC_CTRL_SSBD)
|
||||||
|
fs.setIf(b&(1<<23) != 0, PPIN)
|
||||||
|
fs.setIf(b&(1<<21) != 0, TLB_FLUSH_NESTED)
|
||||||
|
fs.setIf(b&(1<<20) != 0, EFER_LMSLE_UNS)
|
||||||
|
fs.setIf(b&(1<<19) != 0, IBRS_PROVIDES_SMP)
|
||||||
|
fs.setIf(b&(1<<18) != 0, IBRS_PREFERRED)
|
||||||
|
fs.setIf(b&(1<<17) != 0, STIBP_ALWAYSON)
|
||||||
|
fs.setIf(b&(1<<15) != 0, STIBP)
|
||||||
|
fs.setIf(b&(1<<14) != 0, IBRS)
|
||||||
|
fs.setIf((b&(1<<13)) != 0, INT_WBINVD)
|
||||||
|
fs.setIf(b&(1<<12) != 0, IBPB)
|
||||||
fs.setIf((b&(1<<9)) != 0, WBNOINVD)
|
fs.setIf((b&(1<<9)) != 0, WBNOINVD)
|
||||||
|
fs.setIf((b&(1<<8)) != 0, MCOMMIT)
|
||||||
|
fs.setIf((b&(1<<4)) != 0, RDPRU)
|
||||||
|
fs.setIf((b&(1<<3)) != 0, INVLPGB)
|
||||||
|
fs.setIf((b&(1<<1)) != 0, MSRIRC)
|
||||||
|
fs.setIf((b&(1<<0)) != 0, CLZERO)
|
||||||
|
}
|
||||||
|
|
||||||
|
if fs.inSet(SVM) && maxExtendedFunction() >= 0x8000000A {
|
||||||
|
_, _, _, edx := cpuid(0x8000000A)
|
||||||
|
fs.setIf((edx>>0)&1 == 1, SVMNP)
|
||||||
|
fs.setIf((edx>>1)&1 == 1, LBRVIRT)
|
||||||
|
fs.setIf((edx>>2)&1 == 1, SVML)
|
||||||
|
fs.setIf((edx>>3)&1 == 1, NRIPS)
|
||||||
|
fs.setIf((edx>>4)&1 == 1, TSCRATEMSR)
|
||||||
|
fs.setIf((edx>>5)&1 == 1, VMCBCLEAN)
|
||||||
|
fs.setIf((edx>>6)&1 == 1, SVMFBASID)
|
||||||
|
fs.setIf((edx>>7)&1 == 1, SVMDA)
|
||||||
|
fs.setIf((edx>>10)&1 == 1, SVMPF)
|
||||||
|
fs.setIf((edx>>12)&1 == 1, SVMPFT)
|
||||||
|
}
|
||||||
|
|
||||||
|
if maxExtendedFunction() >= 0x8000001a {
|
||||||
|
eax, _, _, _ := cpuid(0x8000001a)
|
||||||
|
fs.setIf((eax>>0)&1 == 1, FP128)
|
||||||
|
fs.setIf((eax>>1)&1 == 1, MOVU)
|
||||||
|
fs.setIf((eax>>2)&1 == 1, FP256)
|
||||||
}
|
}
|
||||||
|
|
||||||
if maxExtendedFunction() >= 0x8000001b && fs.inSet(IBS) {
|
if maxExtendedFunction() >= 0x8000001b && fs.inSet(IBS) {
|
||||||
@ -989,6 +1370,35 @@ func support() flagSet {
|
|||||||
fs.setIf((eax>>5)&1 == 1, IBSBRNTRGT)
|
fs.setIf((eax>>5)&1 == 1, IBSBRNTRGT)
|
||||||
fs.setIf((eax>>6)&1 == 1, IBSOPCNTEXT)
|
fs.setIf((eax>>6)&1 == 1, IBSOPCNTEXT)
|
||||||
fs.setIf((eax>>7)&1 == 1, IBSRIPINVALIDCHK)
|
fs.setIf((eax>>7)&1 == 1, IBSRIPINVALIDCHK)
|
||||||
|
fs.setIf((eax>>8)&1 == 1, IBS_OPFUSE)
|
||||||
|
fs.setIf((eax>>9)&1 == 1, IBS_FETCH_CTLX)
|
||||||
|
fs.setIf((eax>>10)&1 == 1, IBS_OPDATA4) // Doc says "Fixed,0. IBS op data 4 MSR supported", but assuming they mean 1.
|
||||||
|
fs.setIf((eax>>11)&1 == 1, IBS_ZEN4)
|
||||||
|
}
|
||||||
|
|
||||||
|
if maxExtendedFunction() >= 0x8000001f && vend == AMD {
|
||||||
|
a, _, _, _ := cpuid(0x8000001f)
|
||||||
|
fs.setIf((a>>0)&1 == 1, SME)
|
||||||
|
fs.setIf((a>>1)&1 == 1, SEV)
|
||||||
|
fs.setIf((a>>2)&1 == 1, MSR_PAGEFLUSH)
|
||||||
|
fs.setIf((a>>3)&1 == 1, SEV_ES)
|
||||||
|
fs.setIf((a>>4)&1 == 1, SEV_SNP)
|
||||||
|
fs.setIf((a>>5)&1 == 1, VMPL)
|
||||||
|
fs.setIf((a>>10)&1 == 1, SME_COHERENT)
|
||||||
|
fs.setIf((a>>11)&1 == 1, SEV_64BIT)
|
||||||
|
fs.setIf((a>>12)&1 == 1, SEV_RESTRICTED)
|
||||||
|
fs.setIf((a>>13)&1 == 1, SEV_ALTERNATIVE)
|
||||||
|
fs.setIf((a>>14)&1 == 1, SEV_DEBUGSWAP)
|
||||||
|
fs.setIf((a>>15)&1 == 1, IBS_PREVENTHOST)
|
||||||
|
fs.setIf((a>>16)&1 == 1, VTE)
|
||||||
|
fs.setIf((a>>24)&1 == 1, VMSA_REGPROT)
|
||||||
|
}
|
||||||
|
|
||||||
|
if mfi >= 0x21 {
|
||||||
|
// Intel Trusted Domain Extensions Guests have their own cpuid leaf (0x21).
|
||||||
|
_, ebx, ecx, edx := cpuid(0x21)
|
||||||
|
identity := string(valAsString(ebx, edx, ecx))
|
||||||
|
fs.setIf(identity == "IntelTDX ", TDX_GUEST)
|
||||||
}
|
}
|
||||||
|
|
||||||
return fs
|
return fs
|
||||||
|
|||||||
5
vendor/github.com/klauspost/cpuid/v2/cpuid_386.s
generated
vendored
5
vendor/github.com/klauspost/cpuid/v2/cpuid_386.s
generated
vendored
@ -40,3 +40,8 @@ TEXT ·asmRdtscpAsm(SB), 7, $0
|
|||||||
MOVL CX, ecx+8(FP)
|
MOVL CX, ecx+8(FP)
|
||||||
MOVL DX, edx+12(FP)
|
MOVL DX, edx+12(FP)
|
||||||
RET
|
RET
|
||||||
|
|
||||||
|
// func asmDarwinHasAVX512() bool
|
||||||
|
TEXT ·asmDarwinHasAVX512(SB), 7, $0
|
||||||
|
MOVL $0, eax+0(FP)
|
||||||
|
RET
|
||||||
|
|||||||
30
vendor/github.com/klauspost/cpuid/v2/cpuid_amd64.s
generated
vendored
30
vendor/github.com/klauspost/cpuid/v2/cpuid_amd64.s
generated
vendored
@ -40,3 +40,33 @@ TEXT ·asmRdtscpAsm(SB), 7, $0
|
|||||||
MOVL CX, ecx+8(FP)
|
MOVL CX, ecx+8(FP)
|
||||||
MOVL DX, edx+12(FP)
|
MOVL DX, edx+12(FP)
|
||||||
RET
|
RET
|
||||||
|
|
||||||
|
// From https://go-review.googlesource.com/c/sys/+/285572/
|
||||||
|
// func asmDarwinHasAVX512() bool
|
||||||
|
TEXT ·asmDarwinHasAVX512(SB), 7, $0-1
|
||||||
|
MOVB $0, ret+0(FP) // default to false
|
||||||
|
|
||||||
|
#ifdef GOOS_darwin // return if not darwin
|
||||||
|
#ifdef GOARCH_amd64 // return if not amd64
|
||||||
|
// These values from:
|
||||||
|
// https://github.com/apple/darwin-xnu/blob/xnu-4570.1.46/osfmk/i386/cpu_capabilities.h
|
||||||
|
#define commpage64_base_address 0x00007fffffe00000
|
||||||
|
#define commpage64_cpu_capabilities64 (commpage64_base_address+0x010)
|
||||||
|
#define commpage64_version (commpage64_base_address+0x01E)
|
||||||
|
#define hasAVX512F 0x0000004000000000
|
||||||
|
MOVQ $commpage64_version, BX
|
||||||
|
MOVW (BX), AX
|
||||||
|
CMPW AX, $13 // versions < 13 do not support AVX512
|
||||||
|
JL no_avx512
|
||||||
|
MOVQ $commpage64_cpu_capabilities64, BX
|
||||||
|
MOVQ (BX), AX
|
||||||
|
MOVQ $hasAVX512F, CX
|
||||||
|
ANDQ CX, AX
|
||||||
|
JZ no_avx512
|
||||||
|
MOVB $1, ret+0(FP)
|
||||||
|
|
||||||
|
no_avx512:
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
RET
|
||||||
|
|
||||||
|
|||||||
3
vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
generated
vendored
3
vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
generated
vendored
@ -1,6 +1,7 @@
|
|||||||
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
//+build arm64,!gccgo,!noasm,!appengine
|
//go:build arm64 && !gccgo && !noasm && !appengine
|
||||||
|
// +build arm64,!gccgo,!noasm,!appengine
|
||||||
|
|
||||||
package cpuid
|
package cpuid
|
||||||
|
|
||||||
|
|||||||
3
vendor/github.com/klauspost/cpuid/v2/detect_ref.go
generated
vendored
3
vendor/github.com/klauspost/cpuid/v2/detect_ref.go
generated
vendored
@ -1,6 +1,7 @@
|
|||||||
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
//+build !amd64,!386,!arm64 gccgo noasm appengine
|
//go:build (!amd64 && !386 && !arm64) || gccgo || noasm || appengine
|
||||||
|
// +build !amd64,!386,!arm64 gccgo noasm appengine
|
||||||
|
|
||||||
package cpuid
|
package cpuid
|
||||||
|
|
||||||
|
|||||||
9
vendor/github.com/klauspost/cpuid/v2/detect_x86.go
generated
vendored
9
vendor/github.com/klauspost/cpuid/v2/detect_x86.go
generated
vendored
@ -1,6 +1,7 @@
|
|||||||
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
//+build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine
|
//go:build (386 && !gccgo && !noasm && !appengine) || (amd64 && !gccgo && !noasm && !appengine)
|
||||||
|
// +build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine
|
||||||
|
|
||||||
package cpuid
|
package cpuid
|
||||||
|
|
||||||
@ -8,12 +9,14 @@ func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32)
|
|||||||
func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32)
|
func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32)
|
||||||
func asmXgetbv(index uint32) (eax, edx uint32)
|
func asmXgetbv(index uint32) (eax, edx uint32)
|
||||||
func asmRdtscpAsm() (eax, ebx, ecx, edx uint32)
|
func asmRdtscpAsm() (eax, ebx, ecx, edx uint32)
|
||||||
|
func asmDarwinHasAVX512() bool
|
||||||
|
|
||||||
func initCPU() {
|
func initCPU() {
|
||||||
cpuid = asmCpuid
|
cpuid = asmCpuid
|
||||||
cpuidex = asmCpuidex
|
cpuidex = asmCpuidex
|
||||||
xgetbv = asmXgetbv
|
xgetbv = asmXgetbv
|
||||||
rdtscpAsm = asmRdtscpAsm
|
rdtscpAsm = asmRdtscpAsm
|
||||||
|
darwinHasAVX512 = asmDarwinHasAVX512
|
||||||
}
|
}
|
||||||
|
|
||||||
func addInfo(c *CPUInfo, safe bool) {
|
func addInfo(c *CPUInfo, safe bool) {
|
||||||
@ -21,13 +24,13 @@ func addInfo(c *CPUInfo, safe bool) {
|
|||||||
c.maxExFunc = maxExtendedFunction()
|
c.maxExFunc = maxExtendedFunction()
|
||||||
c.BrandName = brandName()
|
c.BrandName = brandName()
|
||||||
c.CacheLine = cacheLine()
|
c.CacheLine = cacheLine()
|
||||||
c.Family, c.Model = familyModel()
|
c.Family, c.Model, c.Stepping = familyModel()
|
||||||
c.featureSet = support()
|
c.featureSet = support()
|
||||||
c.SGX = hasSGX(c.featureSet.inSet(SGX), c.featureSet.inSet(SGXLC))
|
c.SGX = hasSGX(c.featureSet.inSet(SGX), c.featureSet.inSet(SGXLC))
|
||||||
c.ThreadsPerCore = threadsPerCore()
|
c.ThreadsPerCore = threadsPerCore()
|
||||||
c.LogicalCores = logicalCores()
|
c.LogicalCores = logicalCores()
|
||||||
c.PhysicalCores = physicalCores()
|
c.PhysicalCores = physicalCores()
|
||||||
c.VendorID, c.VendorString = vendorID()
|
c.VendorID, c.VendorString = vendorID()
|
||||||
c.Hz = hertz(c.BrandName)
|
|
||||||
c.cacheSize()
|
c.cacheSize()
|
||||||
|
c.frequencies()
|
||||||
}
|
}
|
||||||
|
|||||||
307
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
307
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
@ -13,114 +13,213 @@ func _() {
|
|||||||
_ = x[AMD3DNOW-3]
|
_ = x[AMD3DNOW-3]
|
||||||
_ = x[AMD3DNOWEXT-4]
|
_ = x[AMD3DNOWEXT-4]
|
||||||
_ = x[AMXBF16-5]
|
_ = x[AMXBF16-5]
|
||||||
_ = x[AMXINT8-6]
|
_ = x[AMXFP16-6]
|
||||||
_ = x[AMXTILE-7]
|
_ = x[AMXINT8-7]
|
||||||
_ = x[AVX-8]
|
_ = x[AMXTILE-8]
|
||||||
_ = x[AVX2-9]
|
_ = x[AVX-9]
|
||||||
_ = x[AVX512BF16-10]
|
_ = x[AVX2-10]
|
||||||
_ = x[AVX512BITALG-11]
|
_ = x[AVX512BF16-11]
|
||||||
_ = x[AVX512BW-12]
|
_ = x[AVX512BITALG-12]
|
||||||
_ = x[AVX512CD-13]
|
_ = x[AVX512BW-13]
|
||||||
_ = x[AVX512DQ-14]
|
_ = x[AVX512CD-14]
|
||||||
_ = x[AVX512ER-15]
|
_ = x[AVX512DQ-15]
|
||||||
_ = x[AVX512F-16]
|
_ = x[AVX512ER-16]
|
||||||
_ = x[AVX512IFMA-17]
|
_ = x[AVX512F-17]
|
||||||
_ = x[AVX512PF-18]
|
_ = x[AVX512FP16-18]
|
||||||
_ = x[AVX512VBMI-19]
|
_ = x[AVX512IFMA-19]
|
||||||
_ = x[AVX512VBMI2-20]
|
_ = x[AVX512PF-20]
|
||||||
_ = x[AVX512VL-21]
|
_ = x[AVX512VBMI-21]
|
||||||
_ = x[AVX512VNNI-22]
|
_ = x[AVX512VBMI2-22]
|
||||||
_ = x[AVX512VP2INTERSECT-23]
|
_ = x[AVX512VL-23]
|
||||||
_ = x[AVX512VPOPCNTDQ-24]
|
_ = x[AVX512VNNI-24]
|
||||||
_ = x[AVXSLOW-25]
|
_ = x[AVX512VP2INTERSECT-25]
|
||||||
_ = x[BMI1-26]
|
_ = x[AVX512VPOPCNTDQ-26]
|
||||||
_ = x[BMI2-27]
|
_ = x[AVXIFMA-27]
|
||||||
_ = x[CLDEMOTE-28]
|
_ = x[AVXNECONVERT-28]
|
||||||
_ = x[CLMUL-29]
|
_ = x[AVXSLOW-29]
|
||||||
_ = x[CMOV-30]
|
_ = x[AVXVNNI-30]
|
||||||
_ = x[CX16-31]
|
_ = x[AVXVNNIINT8-31]
|
||||||
_ = x[ENQCMD-32]
|
_ = x[BHI_CTRL-32]
|
||||||
_ = x[ERMS-33]
|
_ = x[BMI1-33]
|
||||||
_ = x[F16C-34]
|
_ = x[BMI2-34]
|
||||||
_ = x[FMA3-35]
|
_ = x[CETIBT-35]
|
||||||
_ = x[FMA4-36]
|
_ = x[CETSS-36]
|
||||||
_ = x[GFNI-37]
|
_ = x[CLDEMOTE-37]
|
||||||
_ = x[HLE-38]
|
_ = x[CLMUL-38]
|
||||||
_ = x[HTT-39]
|
_ = x[CLZERO-39]
|
||||||
_ = x[HYPERVISOR-40]
|
_ = x[CMOV-40]
|
||||||
_ = x[IBPB-41]
|
_ = x[CMPCCXADD-41]
|
||||||
_ = x[IBS-42]
|
_ = x[CMPSB_SCADBS_SHORT-42]
|
||||||
_ = x[IBSBRNTRGT-43]
|
_ = x[CMPXCHG8-43]
|
||||||
_ = x[IBSFETCHSAM-44]
|
_ = x[CPBOOST-44]
|
||||||
_ = x[IBSFFV-45]
|
_ = x[CPPC-45]
|
||||||
_ = x[IBSOPCNT-46]
|
_ = x[CX16-46]
|
||||||
_ = x[IBSOPCNTEXT-47]
|
_ = x[EFER_LMSLE_UNS-47]
|
||||||
_ = x[IBSOPSAM-48]
|
_ = x[ENQCMD-48]
|
||||||
_ = x[IBSRDWROPCNT-49]
|
_ = x[ERMS-49]
|
||||||
_ = x[IBSRIPINVALIDCHK-50]
|
_ = x[F16C-50]
|
||||||
_ = x[LZCNT-51]
|
_ = x[FLUSH_L1D-51]
|
||||||
_ = x[MMX-52]
|
_ = x[FMA3-52]
|
||||||
_ = x[MMXEXT-53]
|
_ = x[FMA4-53]
|
||||||
_ = x[MOVDIR64B-54]
|
_ = x[FP128-54]
|
||||||
_ = x[MOVDIRI-55]
|
_ = x[FP256-55]
|
||||||
_ = x[MPX-56]
|
_ = x[FSRM-56]
|
||||||
_ = x[NX-57]
|
_ = x[FXSR-57]
|
||||||
_ = x[POPCNT-58]
|
_ = x[FXSROPT-58]
|
||||||
_ = x[RDRAND-59]
|
_ = x[GFNI-59]
|
||||||
_ = x[RDSEED-60]
|
_ = x[HLE-60]
|
||||||
_ = x[RDTSCP-61]
|
_ = x[HRESET-61]
|
||||||
_ = x[RTM-62]
|
_ = x[HTT-62]
|
||||||
_ = x[SERIALIZE-63]
|
_ = x[HWA-63]
|
||||||
_ = x[SGX-64]
|
_ = x[HYBRID_CPU-64]
|
||||||
_ = x[SGXLC-65]
|
_ = x[HYPERVISOR-65]
|
||||||
_ = x[SHA-66]
|
_ = x[IA32_ARCH_CAP-66]
|
||||||
_ = x[SSE-67]
|
_ = x[IA32_CORE_CAP-67]
|
||||||
_ = x[SSE2-68]
|
_ = x[IBPB-68]
|
||||||
_ = x[SSE3-69]
|
_ = x[IBRS-69]
|
||||||
_ = x[SSE4-70]
|
_ = x[IBRS_PREFERRED-70]
|
||||||
_ = x[SSE42-71]
|
_ = x[IBRS_PROVIDES_SMP-71]
|
||||||
_ = x[SSE4A-72]
|
_ = x[IBS-72]
|
||||||
_ = x[SSSE3-73]
|
_ = x[IBSBRNTRGT-73]
|
||||||
_ = x[STIBP-74]
|
_ = x[IBSFETCHSAM-74]
|
||||||
_ = x[TBM-75]
|
_ = x[IBSFFV-75]
|
||||||
_ = x[TSXLDTRK-76]
|
_ = x[IBSOPCNT-76]
|
||||||
_ = x[VAES-77]
|
_ = x[IBSOPCNTEXT-77]
|
||||||
_ = x[VMX-78]
|
_ = x[IBSOPSAM-78]
|
||||||
_ = x[VPCLMULQDQ-79]
|
_ = x[IBSRDWROPCNT-79]
|
||||||
_ = x[WAITPKG-80]
|
_ = x[IBSRIPINVALIDCHK-80]
|
||||||
_ = x[WBNOINVD-81]
|
_ = x[IBS_FETCH_CTLX-81]
|
||||||
_ = x[XOP-82]
|
_ = x[IBS_OPDATA4-82]
|
||||||
_ = x[AESARM-83]
|
_ = x[IBS_OPFUSE-83]
|
||||||
_ = x[ARMCPUID-84]
|
_ = x[IBS_PREVENTHOST-84]
|
||||||
_ = x[ASIMD-85]
|
_ = x[IBS_ZEN4-85]
|
||||||
_ = x[ASIMDDP-86]
|
_ = x[IDPRED_CTRL-86]
|
||||||
_ = x[ASIMDHP-87]
|
_ = x[INT_WBINVD-87]
|
||||||
_ = x[ASIMDRDM-88]
|
_ = x[INVLPGB-88]
|
||||||
_ = x[ATOMICS-89]
|
_ = x[LAHF-89]
|
||||||
_ = x[CRC32-90]
|
_ = x[LAM-90]
|
||||||
_ = x[DCPOP-91]
|
_ = x[LBRVIRT-91]
|
||||||
_ = x[EVTSTRM-92]
|
_ = x[LZCNT-92]
|
||||||
_ = x[FCMA-93]
|
_ = x[MCAOVERFLOW-93]
|
||||||
_ = x[FP-94]
|
_ = x[MCDT_NO-94]
|
||||||
_ = x[FPHP-95]
|
_ = x[MCOMMIT-95]
|
||||||
_ = x[GPA-96]
|
_ = x[MD_CLEAR-96]
|
||||||
_ = x[JSCVT-97]
|
_ = x[MMX-97]
|
||||||
_ = x[LRCPC-98]
|
_ = x[MMXEXT-98]
|
||||||
_ = x[PMULL-99]
|
_ = x[MOVBE-99]
|
||||||
_ = x[SHA1-100]
|
_ = x[MOVDIR64B-100]
|
||||||
_ = x[SHA2-101]
|
_ = x[MOVDIRI-101]
|
||||||
_ = x[SHA3-102]
|
_ = x[MOVSB_ZL-102]
|
||||||
_ = x[SHA512-103]
|
_ = x[MOVU-103]
|
||||||
_ = x[SM3-104]
|
_ = x[MPX-104]
|
||||||
_ = x[SM4-105]
|
_ = x[MSRIRC-105]
|
||||||
_ = x[SVE-106]
|
_ = x[MSRLIST-106]
|
||||||
_ = x[lastID-107]
|
_ = x[MSR_PAGEFLUSH-107]
|
||||||
|
_ = x[NRIPS-108]
|
||||||
|
_ = x[NX-109]
|
||||||
|
_ = x[OSXSAVE-110]
|
||||||
|
_ = x[PCONFIG-111]
|
||||||
|
_ = x[POPCNT-112]
|
||||||
|
_ = x[PPIN-113]
|
||||||
|
_ = x[PREFETCHI-114]
|
||||||
|
_ = x[PSFD-115]
|
||||||
|
_ = x[RDPRU-116]
|
||||||
|
_ = x[RDRAND-117]
|
||||||
|
_ = x[RDSEED-118]
|
||||||
|
_ = x[RDTSCP-119]
|
||||||
|
_ = x[RRSBA_CTRL-120]
|
||||||
|
_ = x[RTM-121]
|
||||||
|
_ = x[RTM_ALWAYS_ABORT-122]
|
||||||
|
_ = x[SERIALIZE-123]
|
||||||
|
_ = x[SEV-124]
|
||||||
|
_ = x[SEV_64BIT-125]
|
||||||
|
_ = x[SEV_ALTERNATIVE-126]
|
||||||
|
_ = x[SEV_DEBUGSWAP-127]
|
||||||
|
_ = x[SEV_ES-128]
|
||||||
|
_ = x[SEV_RESTRICTED-129]
|
||||||
|
_ = x[SEV_SNP-130]
|
||||||
|
_ = x[SGX-131]
|
||||||
|
_ = x[SGXLC-132]
|
||||||
|
_ = x[SHA-133]
|
||||||
|
_ = x[SME-134]
|
||||||
|
_ = x[SME_COHERENT-135]
|
||||||
|
_ = x[SPEC_CTRL_SSBD-136]
|
||||||
|
_ = x[SRBDS_CTRL-137]
|
||||||
|
_ = x[SSE-138]
|
||||||
|
_ = x[SSE2-139]
|
||||||
|
_ = x[SSE3-140]
|
||||||
|
_ = x[SSE4-141]
|
||||||
|
_ = x[SSE42-142]
|
||||||
|
_ = x[SSE4A-143]
|
||||||
|
_ = x[SSSE3-144]
|
||||||
|
_ = x[STIBP-145]
|
||||||
|
_ = x[STIBP_ALWAYSON-146]
|
||||||
|
_ = x[STOSB_SHORT-147]
|
||||||
|
_ = x[SUCCOR-148]
|
||||||
|
_ = x[SVM-149]
|
||||||
|
_ = x[SVMDA-150]
|
||||||
|
_ = x[SVMFBASID-151]
|
||||||
|
_ = x[SVML-152]
|
||||||
|
_ = x[SVMNP-153]
|
||||||
|
_ = x[SVMPF-154]
|
||||||
|
_ = x[SVMPFT-155]
|
||||||
|
_ = x[SYSCALL-156]
|
||||||
|
_ = x[SYSEE-157]
|
||||||
|
_ = x[TBM-158]
|
||||||
|
_ = x[TDX_GUEST-159]
|
||||||
|
_ = x[TLB_FLUSH_NESTED-160]
|
||||||
|
_ = x[TME-161]
|
||||||
|
_ = x[TOPEXT-162]
|
||||||
|
_ = x[TSCRATEMSR-163]
|
||||||
|
_ = x[TSXLDTRK-164]
|
||||||
|
_ = x[VAES-165]
|
||||||
|
_ = x[VMCBCLEAN-166]
|
||||||
|
_ = x[VMPL-167]
|
||||||
|
_ = x[VMSA_REGPROT-168]
|
||||||
|
_ = x[VMX-169]
|
||||||
|
_ = x[VPCLMULQDQ-170]
|
||||||
|
_ = x[VTE-171]
|
||||||
|
_ = x[WAITPKG-172]
|
||||||
|
_ = x[WBNOINVD-173]
|
||||||
|
_ = x[WRMSRNS-174]
|
||||||
|
_ = x[X87-175]
|
||||||
|
_ = x[XGETBV1-176]
|
||||||
|
_ = x[XOP-177]
|
||||||
|
_ = x[XSAVE-178]
|
||||||
|
_ = x[XSAVEC-179]
|
||||||
|
_ = x[XSAVEOPT-180]
|
||||||
|
_ = x[XSAVES-181]
|
||||||
|
_ = x[AESARM-182]
|
||||||
|
_ = x[ARMCPUID-183]
|
||||||
|
_ = x[ASIMD-184]
|
||||||
|
_ = x[ASIMDDP-185]
|
||||||
|
_ = x[ASIMDHP-186]
|
||||||
|
_ = x[ASIMDRDM-187]
|
||||||
|
_ = x[ATOMICS-188]
|
||||||
|
_ = x[CRC32-189]
|
||||||
|
_ = x[DCPOP-190]
|
||||||
|
_ = x[EVTSTRM-191]
|
||||||
|
_ = x[FCMA-192]
|
||||||
|
_ = x[FP-193]
|
||||||
|
_ = x[FPHP-194]
|
||||||
|
_ = x[GPA-195]
|
||||||
|
_ = x[JSCVT-196]
|
||||||
|
_ = x[LRCPC-197]
|
||||||
|
_ = x[PMULL-198]
|
||||||
|
_ = x[SHA1-199]
|
||||||
|
_ = x[SHA2-200]
|
||||||
|
_ = x[SHA3-201]
|
||||||
|
_ = x[SHA512-202]
|
||||||
|
_ = x[SM3-203]
|
||||||
|
_ = x[SM4-204]
|
||||||
|
_ = x[SVE-205]
|
||||||
|
_ = x[lastID-206]
|
||||||
_ = x[firstID-0]
|
_ = x[firstID-0]
|
||||||
}
|
}
|
||||||
|
|
||||||
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXSLOWBMI1BMI2CLDEMOTECLMULCMOVCX16ENQCMDERMSF16CFMA3FMA4GFNIHLEHTTHYPERVISORIBPBIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKLZCNTMMXMMXEXTMOVDIR64BMOVDIRIMPXNXPOPCNTRDRANDRDSEEDRDTSCPRTMSERIALIZESGXSGXLCSHASSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPTBMTSXLDTRKVAESVMXVPCLMULQDQWAITPKGWBNOINVDXOPAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
||||||
|
|
||||||
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 58, 62, 72, 84, 92, 100, 108, 116, 123, 133, 141, 151, 162, 170, 180, 198, 213, 220, 224, 228, 236, 241, 245, 249, 255, 259, 263, 267, 271, 275, 278, 281, 291, 295, 298, 308, 319, 325, 333, 344, 352, 364, 380, 385, 388, 394, 403, 410, 413, 415, 421, 427, 433, 439, 442, 451, 454, 459, 462, 465, 469, 473, 477, 482, 487, 492, 497, 500, 508, 512, 515, 525, 532, 540, 543, 549, 557, 562, 569, 576, 584, 591, 596, 601, 608, 612, 614, 618, 621, 626, 631, 636, 640, 644, 648, 654, 657, 660, 663, 669}
|
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 65, 69, 79, 91, 99, 107, 115, 123, 130, 140, 150, 158, 168, 179, 187, 197, 215, 230, 237, 249, 256, 263, 274, 282, 286, 290, 296, 301, 309, 314, 320, 324, 333, 351, 359, 366, 370, 374, 388, 394, 398, 402, 411, 415, 419, 424, 429, 433, 437, 444, 448, 451, 457, 460, 463, 473, 483, 496, 509, 513, 517, 531, 548, 551, 561, 572, 578, 586, 597, 605, 617, 633, 647, 658, 668, 683, 691, 702, 712, 719, 723, 726, 733, 738, 749, 756, 763, 771, 774, 780, 785, 794, 801, 809, 813, 816, 822, 829, 842, 847, 849, 856, 863, 869, 873, 882, 886, 891, 897, 903, 909, 919, 922, 938, 947, 950, 959, 974, 987, 993, 1007, 1014, 1017, 1022, 1025, 1028, 1040, 1054, 1064, 1067, 1071, 1075, 1079, 1084, 1089, 1094, 1099, 1113, 1124, 1130, 1133, 1138, 1147, 1151, 1156, 1161, 1167, 1174, 1179, 1182, 1191, 1207, 1210, 1216, 1226, 1234, 1238, 1247, 1251, 1263, 1266, 1276, 1279, 1286, 1294, 1301, 1304, 1311, 1314, 1319, 1325, 1333, 1339, 1345, 1353, 1358, 1365, 1372, 1380, 1387, 1392, 1397, 1404, 1408, 1410, 1414, 1417, 1422, 1427, 1432, 1436, 1440, 1444, 1450, 1453, 1456, 1459, 1465}
|
||||||
|
|
||||||
func (i FeatureID) String() string {
|
func (i FeatureID) String() string {
|
||||||
if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
|
if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
|
||||||
|
|||||||
108
vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
generated
vendored
108
vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
generated
vendored
@ -2,14 +2,120 @@
|
|||||||
|
|
||||||
package cpuid
|
package cpuid
|
||||||
|
|
||||||
import "runtime"
|
import (
|
||||||
|
"runtime"
|
||||||
|
"strings"
|
||||||
|
|
||||||
|
"golang.org/x/sys/unix"
|
||||||
|
)
|
||||||
|
|
||||||
func detectOS(c *CPUInfo) bool {
|
func detectOS(c *CPUInfo) bool {
|
||||||
|
if runtime.GOOS != "ios" {
|
||||||
|
tryToFillCPUInfoFomSysctl(c)
|
||||||
|
}
|
||||||
// There are no hw.optional sysctl values for the below features on Mac OS 11.0
|
// There are no hw.optional sysctl values for the below features on Mac OS 11.0
|
||||||
// to detect their supported state dynamically. Assume the CPU features that
|
// to detect their supported state dynamically. Assume the CPU features that
|
||||||
// Apple Silicon M1 supports to be available as a minimal set of features
|
// Apple Silicon M1 supports to be available as a minimal set of features
|
||||||
// to all Go programs running on darwin/arm64.
|
// to all Go programs running on darwin/arm64.
|
||||||
// TODO: Add more if we know them.
|
// TODO: Add more if we know them.
|
||||||
c.featureSet.setIf(runtime.GOOS != "ios", AESARM, PMULL, SHA1, SHA2)
|
c.featureSet.setIf(runtime.GOOS != "ios", AESARM, PMULL, SHA1, SHA2)
|
||||||
|
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
|
|
||||||
|
func sysctlGetBool(name string) bool {
|
||||||
|
value, err := unix.SysctlUint32(name)
|
||||||
|
if err != nil {
|
||||||
|
return false
|
||||||
|
}
|
||||||
|
return value != 0
|
||||||
|
}
|
||||||
|
|
||||||
|
func sysctlGetString(name string) string {
|
||||||
|
value, err := unix.Sysctl(name)
|
||||||
|
if err != nil {
|
||||||
|
return ""
|
||||||
|
}
|
||||||
|
return value
|
||||||
|
}
|
||||||
|
|
||||||
|
func sysctlGetInt(unknown int, names ...string) int {
|
||||||
|
for _, name := range names {
|
||||||
|
value, err := unix.SysctlUint32(name)
|
||||||
|
if err != nil {
|
||||||
|
continue
|
||||||
|
}
|
||||||
|
if value != 0 {
|
||||||
|
return int(value)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return unknown
|
||||||
|
}
|
||||||
|
|
||||||
|
func sysctlGetInt64(unknown int, names ...string) int {
|
||||||
|
for _, name := range names {
|
||||||
|
value64, err := unix.SysctlUint64(name)
|
||||||
|
if err != nil {
|
||||||
|
continue
|
||||||
|
}
|
||||||
|
if int(value64) != unknown {
|
||||||
|
return int(value64)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return unknown
|
||||||
|
}
|
||||||
|
|
||||||
|
func setFeature(c *CPUInfo, name string, feature FeatureID) {
|
||||||
|
c.featureSet.setIf(sysctlGetBool(name), feature)
|
||||||
|
}
|
||||||
|
func tryToFillCPUInfoFomSysctl(c *CPUInfo) {
|
||||||
|
c.BrandName = sysctlGetString("machdep.cpu.brand_string")
|
||||||
|
|
||||||
|
if len(c.BrandName) != 0 {
|
||||||
|
c.VendorString = strings.Fields(c.BrandName)[0]
|
||||||
|
}
|
||||||
|
|
||||||
|
c.PhysicalCores = sysctlGetInt(runtime.NumCPU(), "hw.physicalcpu")
|
||||||
|
c.ThreadsPerCore = sysctlGetInt(1, "machdep.cpu.thread_count", "kern.num_threads") /
|
||||||
|
sysctlGetInt(1, "hw.physicalcpu")
|
||||||
|
c.LogicalCores = sysctlGetInt(runtime.NumCPU(), "machdep.cpu.core_count")
|
||||||
|
c.Family = sysctlGetInt(0, "machdep.cpu.family", "hw.cpufamily")
|
||||||
|
c.Model = sysctlGetInt(0, "machdep.cpu.model")
|
||||||
|
c.CacheLine = sysctlGetInt64(0, "hw.cachelinesize")
|
||||||
|
c.Cache.L1I = sysctlGetInt64(-1, "hw.l1icachesize")
|
||||||
|
c.Cache.L1D = sysctlGetInt64(-1, "hw.l1dcachesize")
|
||||||
|
c.Cache.L2 = sysctlGetInt64(-1, "hw.l2cachesize")
|
||||||
|
c.Cache.L3 = sysctlGetInt64(-1, "hw.l3cachesize")
|
||||||
|
|
||||||
|
// from https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_AES", AESARM)
|
||||||
|
setFeature(c, "hw.optional.AdvSIMD", ASIMD)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_DotProd", ASIMDDP)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_RDM", ASIMDRDM)
|
||||||
|
setFeature(c, "hw.optional.FEAT_CRC32", CRC32)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_DPB", DCPOP)
|
||||||
|
// setFeature(c, "", EVTSTRM)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_FCMA", FCMA)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_FP", FP)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_FP16", FPHP)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_PAuth", GPA)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_JSCVT", JSCVT)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_LRCPC", LRCPC)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_PMULL", PMULL)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_SHA1", SHA1)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_SHA256", SHA2)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_SHA3", SHA3)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_SHA512", SHA512)
|
||||||
|
// setFeature(c, "", SM3)
|
||||||
|
// setFeature(c, "", SM4)
|
||||||
|
setFeature(c, "hw.optional.arm.FEAT_SVE", SVE)
|
||||||
|
|
||||||
|
// from empirical observation
|
||||||
|
setFeature(c, "hw.optional.AdvSIMD_HPFPCvt", ASIMDHP)
|
||||||
|
setFeature(c, "hw.optional.armv8_1_atomics", ATOMICS)
|
||||||
|
setFeature(c, "hw.optional.floatingpoint", FP)
|
||||||
|
setFeature(c, "hw.optional.armv8_2_sha3", SHA3)
|
||||||
|
setFeature(c, "hw.optional.armv8_2_sha512", SHA512)
|
||||||
|
setFeature(c, "hw.optional.armv8_3_compnum", FCMA)
|
||||||
|
setFeature(c, "hw.optional.armv8_crc32", CRC32)
|
||||||
|
}
|
||||||
|
|||||||
33
vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
generated
vendored
33
vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
generated
vendored
@ -11,7 +11,6 @@ import (
|
|||||||
"encoding/binary"
|
"encoding/binary"
|
||||||
"io/ioutil"
|
"io/ioutil"
|
||||||
"runtime"
|
"runtime"
|
||||||
"unsafe"
|
|
||||||
)
|
)
|
||||||
|
|
||||||
// HWCAP bits.
|
// HWCAP bits.
|
||||||
@ -42,12 +41,9 @@ const (
|
|||||||
hwcap_ASIMDFHM = 1 << 23
|
hwcap_ASIMDFHM = 1 << 23
|
||||||
)
|
)
|
||||||
|
|
||||||
//go:linkname hwcap internal/cpu.HWCap
|
|
||||||
var hwcap uint
|
|
||||||
|
|
||||||
func detectOS(c *CPUInfo) bool {
|
func detectOS(c *CPUInfo) bool {
|
||||||
// For now assuming no hyperthreading is reasonable.
|
// For now assuming no hyperthreading is reasonable.
|
||||||
c.LogicalCores = int(getproccount())
|
c.LogicalCores = runtime.NumCPU()
|
||||||
c.PhysicalCores = c.LogicalCores
|
c.PhysicalCores = c.LogicalCores
|
||||||
c.ThreadsPerCore = 1
|
c.ThreadsPerCore = 1
|
||||||
if hwcap == 0 {
|
if hwcap == 0 {
|
||||||
@ -132,30 +128,3 @@ func detectOS(c *CPUInfo) bool {
|
|||||||
func isSet(hwc uint, value uint) bool {
|
func isSet(hwc uint, value uint) bool {
|
||||||
return hwc&value != 0
|
return hwc&value != 0
|
||||||
}
|
}
|
||||||
|
|
||||||
//go:noescape
|
|
||||||
//go:linkname sched_getaffinity runtime.sched_getaffinity
|
|
||||||
func sched_getaffinity(pid, len uintptr, buf *byte) int32
|
|
||||||
|
|
||||||
func getproccount() int32 {
|
|
||||||
// This buffer is huge (8 kB) but we are on the system stack
|
|
||||||
// and there should be plenty of space (64 kB).
|
|
||||||
// Also this is a leaf, so we're not holding up the memory for long.
|
|
||||||
const maxCPUs = 64 * 1024
|
|
||||||
var buf [maxCPUs / 8]byte
|
|
||||||
r := sched_getaffinity(0, unsafe.Sizeof(buf), &buf[0])
|
|
||||||
if r < 0 {
|
|
||||||
return 0
|
|
||||||
}
|
|
||||||
n := int32(0)
|
|
||||||
for _, v := range buf[:r] {
|
|
||||||
for v != 0 {
|
|
||||||
n += int32(v & 1)
|
|
||||||
v >>= 1
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if n == 0 {
|
|
||||||
n = 1
|
|
||||||
}
|
|
||||||
return n
|
|
||||||
}
|
|
||||||
|
|||||||
11
vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go
generated
vendored
11
vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go
generated
vendored
@ -1,11 +1,16 @@
|
|||||||
// Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file.
|
// Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
// +build arm64
|
//go:build arm64 && !linux && !darwin
|
||||||
// +build !linux
|
// +build arm64,!linux,!darwin
|
||||||
// +build !darwin
|
|
||||||
|
|
||||||
package cpuid
|
package cpuid
|
||||||
|
|
||||||
|
import "runtime"
|
||||||
|
|
||||||
func detectOS(c *CPUInfo) bool {
|
func detectOS(c *CPUInfo) bool {
|
||||||
|
c.PhysicalCores = runtime.NumCPU()
|
||||||
|
// For now assuming 1 thread per core...
|
||||||
|
c.ThreadsPerCore = 1
|
||||||
|
c.LogicalCores = c.PhysicalCores
|
||||||
return false
|
return false
|
||||||
}
|
}
|
||||||
|
|||||||
8
vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go
generated
vendored
Normal file
8
vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go
generated
vendored
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
// Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
|
//go:build nounsafe
|
||||||
|
// +build nounsafe
|
||||||
|
|
||||||
|
package cpuid
|
||||||
|
|
||||||
|
var hwcap uint
|
||||||
11
vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go
generated
vendored
Normal file
11
vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go
generated
vendored
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
// Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file.
|
||||||
|
|
||||||
|
//go:build !nounsafe
|
||||||
|
// +build !nounsafe
|
||||||
|
|
||||||
|
package cpuid
|
||||||
|
|
||||||
|
import _ "unsafe" // needed for go:linkname
|
||||||
|
|
||||||
|
//go:linkname hwcap internal/cpu.HWCap
|
||||||
|
var hwcap uint
|
||||||
8
vendor/github.com/klauspost/cpuid/v2/test-architectures.sh
generated
vendored
8
vendor/github.com/klauspost/cpuid/v2/test-architectures.sh
generated
vendored
@ -5,11 +5,11 @@ set -e
|
|||||||
go tool dist list | while IFS=/ read os arch; do
|
go tool dist list | while IFS=/ read os arch; do
|
||||||
echo "Checking $os/$arch..."
|
echo "Checking $os/$arch..."
|
||||||
echo " normal"
|
echo " normal"
|
||||||
GOARCH=$arch GOOS=$os go build -o /dev/null ./...
|
GOARCH=$arch GOOS=$os go build -o /dev/null .
|
||||||
echo " noasm"
|
echo " noasm"
|
||||||
GOARCH=$arch GOOS=$os go build -tags noasm -o /dev/null ./...
|
GOARCH=$arch GOOS=$os go build -tags noasm -o /dev/null .
|
||||||
echo " appengine"
|
echo " appengine"
|
||||||
GOARCH=$arch GOOS=$os go build -tags appengine -o /dev/null ./...
|
GOARCH=$arch GOOS=$os go build -tags appengine -o /dev/null .
|
||||||
echo " noasm,appengine"
|
echo " noasm,appengine"
|
||||||
GOARCH=$arch GOOS=$os go build -tags 'appengine noasm' -o /dev/null ./...
|
GOARCH=$arch GOOS=$os go build -tags 'appengine noasm' -o /dev/null .
|
||||||
done
|
done
|
||||||
|
|||||||
6
vendor/github.com/minio/sha256-simd/cpuid_other.go
generated
vendored
6
vendor/github.com/minio/sha256-simd/cpuid_other.go
generated
vendored
@ -23,6 +23,11 @@ import (
|
|||||||
"github.com/klauspost/cpuid/v2"
|
"github.com/klauspost/cpuid/v2"
|
||||||
)
|
)
|
||||||
|
|
||||||
|
var (
|
||||||
|
hasIntelSha = runtime.GOARCH == "amd64" && cpuid.CPU.Supports(cpuid.SHA, cpuid.SSSE3, cpuid.SSE4)
|
||||||
|
hasAvx512 = cpuid.CPU.Supports(cpuid.AVX512F, cpuid.AVX512DQ, cpuid.AVX512BW, cpuid.AVX512VL)
|
||||||
|
)
|
||||||
|
|
||||||
func hasArmSha2() bool {
|
func hasArmSha2() bool {
|
||||||
if cpuid.CPU.Has(cpuid.SHA2) {
|
if cpuid.CPU.Has(cpuid.SHA2) {
|
||||||
return true
|
return true
|
||||||
@ -42,5 +47,4 @@ func hasArmSha2() bool {
|
|||||||
return false
|
return false
|
||||||
}
|
}
|
||||||
return bytes.Contains(cpuInfo, []byte(sha256Feature))
|
return bytes.Contains(cpuInfo, []byte(sha256Feature))
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|||||||
131
vendor/github.com/minio/sha256-simd/sha256.go
generated
vendored
131
vendor/github.com/minio/sha256-simd/sha256.go
generated
vendored
@ -19,10 +19,8 @@ package sha256
|
|||||||
import (
|
import (
|
||||||
"crypto/sha256"
|
"crypto/sha256"
|
||||||
"encoding/binary"
|
"encoding/binary"
|
||||||
|
"errors"
|
||||||
"hash"
|
"hash"
|
||||||
"runtime"
|
|
||||||
|
|
||||||
"github.com/klauspost/cpuid/v2"
|
|
||||||
)
|
)
|
||||||
|
|
||||||
// Size - The size of a SHA256 checksum in bytes.
|
// Size - The size of a SHA256 checksum in bytes.
|
||||||
@ -68,42 +66,34 @@ func (d *digest) Reset() {
|
|||||||
type blockfuncType int
|
type blockfuncType int
|
||||||
|
|
||||||
const (
|
const (
|
||||||
blockfuncGeneric blockfuncType = iota
|
blockfuncStdlib blockfuncType = iota
|
||||||
blockfuncSha blockfuncType = iota
|
blockfuncIntelSha
|
||||||
blockfuncArm blockfuncType = iota
|
blockfuncArmSha2
|
||||||
|
blockfuncForceGeneric = -1
|
||||||
)
|
)
|
||||||
|
|
||||||
var blockfunc blockfuncType
|
var blockfunc blockfuncType
|
||||||
|
|
||||||
func init() {
|
func init() {
|
||||||
blockfunc = blockfuncGeneric
|
|
||||||
switch {
|
switch {
|
||||||
case hasSHAExtensions():
|
case hasIntelSha:
|
||||||
blockfunc = blockfuncSha
|
blockfunc = blockfuncIntelSha
|
||||||
case hasArmSha2():
|
case hasArmSha2():
|
||||||
blockfunc = blockfuncArm
|
blockfunc = blockfuncArmSha2
|
||||||
default:
|
|
||||||
blockfunc = blockfuncGeneric
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
var avx512 = cpuid.CPU.Supports(cpuid.AVX512F, cpuid.AVX512DQ, cpuid.AVX512BW, cpuid.AVX512VL)
|
|
||||||
|
|
||||||
// hasSHAExtensions return whether the cpu supports SHA extensions.
|
|
||||||
func hasSHAExtensions() bool {
|
|
||||||
return cpuid.CPU.Supports(cpuid.SHA, cpuid.SSSE3, cpuid.SSE4) && runtime.GOARCH == "amd64"
|
|
||||||
}
|
|
||||||
|
|
||||||
// New returns a new hash.Hash computing the SHA256 checksum.
|
// New returns a new hash.Hash computing the SHA256 checksum.
|
||||||
func New() hash.Hash {
|
func New() hash.Hash {
|
||||||
if blockfunc != blockfuncGeneric {
|
if blockfunc == blockfuncStdlib {
|
||||||
d := new(digest)
|
// Fallback to the standard golang implementation
|
||||||
d.Reset()
|
// if no features were found.
|
||||||
return d
|
return sha256.New()
|
||||||
}
|
}
|
||||||
// Fallback to the standard golang implementation
|
|
||||||
// if no features were found.
|
d := new(digest)
|
||||||
return sha256.New()
|
d.Reset()
|
||||||
|
return d
|
||||||
}
|
}
|
||||||
|
|
||||||
// Sum256 - single caller sha256 helper
|
// Sum256 - single caller sha256 helper
|
||||||
@ -272,11 +262,11 @@ func (d *digest) checkSum() (digest [Size]byte) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
func block(dig *digest, p []byte) {
|
func block(dig *digest, p []byte) {
|
||||||
if blockfunc == blockfuncSha {
|
if blockfunc == blockfuncIntelSha {
|
||||||
blockShaGo(dig, p)
|
blockIntelShaGo(dig, p)
|
||||||
} else if blockfunc == blockfuncArm {
|
} else if blockfunc == blockfuncArmSha2 {
|
||||||
blockArmGo(dig, p)
|
blockArmSha2Go(dig, p)
|
||||||
} else if blockfunc == blockfuncGeneric {
|
} else {
|
||||||
blockGeneric(dig, p)
|
blockGeneric(dig, p)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -397,3 +387,82 @@ var _K = []uint32{
|
|||||||
0xbef9a3f7,
|
0xbef9a3f7,
|
||||||
0xc67178f2,
|
0xc67178f2,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
const (
|
||||||
|
magic256 = "sha\x03"
|
||||||
|
marshaledSize = len(magic256) + 8*4 + chunk + 8
|
||||||
|
)
|
||||||
|
|
||||||
|
func (d *digest) MarshalBinary() ([]byte, error) {
|
||||||
|
b := make([]byte, 0, marshaledSize)
|
||||||
|
b = append(b, magic256...)
|
||||||
|
b = appendUint32(b, d.h[0])
|
||||||
|
b = appendUint32(b, d.h[1])
|
||||||
|
b = appendUint32(b, d.h[2])
|
||||||
|
b = appendUint32(b, d.h[3])
|
||||||
|
b = appendUint32(b, d.h[4])
|
||||||
|
b = appendUint32(b, d.h[5])
|
||||||
|
b = appendUint32(b, d.h[6])
|
||||||
|
b = appendUint32(b, d.h[7])
|
||||||
|
b = append(b, d.x[:d.nx]...)
|
||||||
|
b = b[:len(b)+len(d.x)-d.nx] // already zero
|
||||||
|
b = appendUint64(b, d.len)
|
||||||
|
return b, nil
|
||||||
|
}
|
||||||
|
|
||||||
|
func (d *digest) UnmarshalBinary(b []byte) error {
|
||||||
|
if len(b) < len(magic256) || string(b[:len(magic256)]) != magic256 {
|
||||||
|
return errors.New("crypto/sha256: invalid hash state identifier")
|
||||||
|
}
|
||||||
|
if len(b) != marshaledSize {
|
||||||
|
return errors.New("crypto/sha256: invalid hash state size")
|
||||||
|
}
|
||||||
|
b = b[len(magic256):]
|
||||||
|
b, d.h[0] = consumeUint32(b)
|
||||||
|
b, d.h[1] = consumeUint32(b)
|
||||||
|
b, d.h[2] = consumeUint32(b)
|
||||||
|
b, d.h[3] = consumeUint32(b)
|
||||||
|
b, d.h[4] = consumeUint32(b)
|
||||||
|
b, d.h[5] = consumeUint32(b)
|
||||||
|
b, d.h[6] = consumeUint32(b)
|
||||||
|
b, d.h[7] = consumeUint32(b)
|
||||||
|
b = b[copy(d.x[:], b):]
|
||||||
|
b, d.len = consumeUint64(b)
|
||||||
|
d.nx = int(d.len % chunk)
|
||||||
|
return nil
|
||||||
|
}
|
||||||
|
|
||||||
|
func appendUint32(b []byte, v uint32) []byte {
|
||||||
|
return append(b,
|
||||||
|
byte(v>>24),
|
||||||
|
byte(v>>16),
|
||||||
|
byte(v>>8),
|
||||||
|
byte(v),
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
func appendUint64(b []byte, v uint64) []byte {
|
||||||
|
return append(b,
|
||||||
|
byte(v>>56),
|
||||||
|
byte(v>>48),
|
||||||
|
byte(v>>40),
|
||||||
|
byte(v>>32),
|
||||||
|
byte(v>>24),
|
||||||
|
byte(v>>16),
|
||||||
|
byte(v>>8),
|
||||||
|
byte(v),
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
func consumeUint64(b []byte) ([]byte, uint64) {
|
||||||
|
_ = b[7]
|
||||||
|
x := uint64(b[7]) | uint64(b[6])<<8 | uint64(b[5])<<16 | uint64(b[4])<<24 |
|
||||||
|
uint64(b[3])<<32 | uint64(b[2])<<40 | uint64(b[1])<<48 | uint64(b[0])<<56
|
||||||
|
return b[8:], x
|
||||||
|
}
|
||||||
|
|
||||||
|
func consumeUint32(b []byte) ([]byte, uint32) {
|
||||||
|
_ = b[3]
|
||||||
|
x := uint32(b[3]) | uint32(b[2])<<8 | uint32(b[1])<<16 | uint32(b[0])<<24
|
||||||
|
return b[4:], x
|
||||||
|
}
|
||||||
|
|||||||
3
vendor/github.com/minio/sha256-simd/sha256blockAvx512_amd64.go
generated
vendored
3
vendor/github.com/minio/sha256-simd/sha256blockAvx512_amd64.go
generated
vendored
@ -1,4 +1,5 @@
|
|||||||
//+build !noasm,!appengine,gc
|
//go:build !noasm && !appengine && gc
|
||||||
|
// +build !noasm,!appengine,gc
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minio Cloud Storage, (C) 2017 Minio, Inc.
|
* Minio Cloud Storage, (C) 2017 Minio, Inc.
|
||||||
|
|||||||
2
vendor/github.com/minio/sha256-simd/sha256blockAvx512_amd64.s
generated
vendored
2
vendor/github.com/minio/sha256-simd/sha256blockAvx512_amd64.s
generated
vendored
@ -1,4 +1,4 @@
|
|||||||
//+build !noasm,!appengine
|
//+build !noasm,!appengine,gc
|
||||||
|
|
||||||
TEXT ·sha256X16Avx512(SB), 7, $0
|
TEXT ·sha256X16Avx512(SB), 7, $0
|
||||||
MOVQ digests+0(FP), DI
|
MOVQ digests+0(FP), DI
|
||||||
|
|||||||
6
vendor/github.com/minio/sha256-simd/sha256blockSha_amd64.go
generated
vendored
6
vendor/github.com/minio/sha256-simd/sha256blockSha_amd64.go
generated
vendored
@ -1,6 +0,0 @@
|
|||||||
//+build !noasm,!appengine,gc
|
|
||||||
|
|
||||||
package sha256
|
|
||||||
|
|
||||||
//go:noescape
|
|
||||||
func blockSha(h *[8]uint32, message []uint8)
|
|
||||||
14
vendor/github.com/minio/sha256-simd/sha256block_amd64.go
generated
vendored
14
vendor/github.com/minio/sha256-simd/sha256block_amd64.go
generated
vendored
@ -1,4 +1,5 @@
|
|||||||
//+build !noasm,!appengine,gc
|
//go:build !noasm && !appengine && gc
|
||||||
|
// +build !noasm,!appengine,gc
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minio Cloud Storage, (C) 2016 Minio, Inc.
|
* Minio Cloud Storage, (C) 2016 Minio, Inc.
|
||||||
@ -18,10 +19,13 @@
|
|||||||
|
|
||||||
package sha256
|
package sha256
|
||||||
|
|
||||||
func blockArmGo(dig *digest, p []byte) {
|
func blockArmSha2Go(dig *digest, p []byte) {
|
||||||
panic("blockArmGo called unexpectedly")
|
panic("blockArmSha2Go called unexpectedly")
|
||||||
}
|
}
|
||||||
|
|
||||||
func blockShaGo(dig *digest, p []byte) {
|
//go:noescape
|
||||||
blockSha(&dig.h, p)
|
func blockIntelSha(h *[8]uint32, message []uint8)
|
||||||
|
|
||||||
|
func blockIntelShaGo(dig *digest, p []byte) {
|
||||||
|
blockIntelSha(&dig.h, p)
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,4 +1,4 @@
|
|||||||
//+build !noasm,!appengine
|
//+build !noasm,!appengine,gc
|
||||||
|
|
||||||
// SHA intrinsic version of SHA256
|
// SHA intrinsic version of SHA256
|
||||||
|
|
||||||
@ -106,7 +106,7 @@ GLOBL SHUF_MASK<>(SB), RODATA|NOPTR, $16
|
|||||||
// X13 saved hash state // CDGH
|
// X13 saved hash state // CDGH
|
||||||
// X15 data shuffle mask (constant)
|
// X15 data shuffle mask (constant)
|
||||||
|
|
||||||
TEXT ·blockSha(SB), NOSPLIT, $0-32
|
TEXT ·blockIntelSha(SB), NOSPLIT, $0-32
|
||||||
MOVQ h+0(FP), DX
|
MOVQ h+0(FP), DX
|
||||||
MOVQ message_base+8(FP), SI
|
MOVQ message_base+8(FP), SI
|
||||||
MOVQ message_len+16(FP), DI
|
MOVQ message_len+16(FP), DI
|
||||||
13
vendor/github.com/minio/sha256-simd/sha256block_arm64.go
generated
vendored
13
vendor/github.com/minio/sha256-simd/sha256block_arm64.go
generated
vendored
@ -1,4 +1,5 @@
|
|||||||
//+build !noasm,!appengine,gc
|
//go:build !noasm && !appengine && gc
|
||||||
|
// +build !noasm,!appengine,gc
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minio Cloud Storage, (C) 2016 Minio, Inc.
|
* Minio Cloud Storage, (C) 2016 Minio, Inc.
|
||||||
@ -18,18 +19,18 @@
|
|||||||
|
|
||||||
package sha256
|
package sha256
|
||||||
|
|
||||||
func blockShaGo(dig *digest, p []byte) {
|
func blockIntelShaGo(dig *digest, p []byte) {
|
||||||
panic("blockShaGoc called unexpectedly")
|
panic("blockIntelShaGo called unexpectedly")
|
||||||
}
|
}
|
||||||
|
|
||||||
//go:noescape
|
//go:noescape
|
||||||
func blockArm(h []uint32, message []uint8)
|
func blockArmSha2(h []uint32, message []uint8)
|
||||||
|
|
||||||
func blockArmGo(dig *digest, p []byte) {
|
func blockArmSha2Go(dig *digest, p []byte) {
|
||||||
|
|
||||||
h := []uint32{dig.h[0], dig.h[1], dig.h[2], dig.h[3], dig.h[4], dig.h[5], dig.h[6], dig.h[7]}
|
h := []uint32{dig.h[0], dig.h[1], dig.h[2], dig.h[3], dig.h[4], dig.h[5], dig.h[6], dig.h[7]}
|
||||||
|
|
||||||
blockArm(h[:], p[:])
|
blockArmSha2(h[:], p[:])
|
||||||
|
|
||||||
dig.h[0], dig.h[1], dig.h[2], dig.h[3], dig.h[4], dig.h[5], dig.h[6], dig.h[7] = h[0], h[1], h[2], h[3], h[4],
|
dig.h[0], dig.h[1], dig.h[2], dig.h[3], dig.h[4], dig.h[5], dig.h[6], dig.h[7] = h[0], h[1], h[2], h[3], h[4],
|
||||||
h[5], h[6], h[7]
|
h[5], h[6], h[7]
|
||||||
|
|||||||
4
vendor/github.com/minio/sha256-simd/sha256block_arm64.s
generated
vendored
4
vendor/github.com/minio/sha256-simd/sha256block_arm64.s
generated
vendored
@ -1,4 +1,4 @@
|
|||||||
//+build !noasm,!appengine
|
//+build !noasm,!appengine,gc
|
||||||
|
|
||||||
// ARM64 version of SHA256
|
// ARM64 version of SHA256
|
||||||
|
|
||||||
@ -25,7 +25,7 @@
|
|||||||
// their Plan9 equivalents
|
// their Plan9 equivalents
|
||||||
//
|
//
|
||||||
|
|
||||||
TEXT ·blockArm(SB), 7, $0
|
TEXT ·blockArmSha2(SB), 7, $0
|
||||||
MOVD h+0(FP), R0
|
MOVD h+0(FP), R0
|
||||||
MOVD message+24(FP), R1
|
MOVD message+24(FP), R1
|
||||||
MOVD message_len+32(FP), R2 // length of message
|
MOVD message_len+32(FP), R2 // length of message
|
||||||
|
|||||||
11
vendor/github.com/minio/sha256-simd/sha256block_other.go
generated
vendored
11
vendor/github.com/minio/sha256-simd/sha256block_other.go
generated
vendored
@ -1,4 +1,5 @@
|
|||||||
//+build appengine noasm !amd64,!arm64 !gc
|
//go:build appengine || noasm || (!amd64 && !arm64) || !gc
|
||||||
|
// +build appengine noasm !amd64,!arm64 !gc
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minio Cloud Storage, (C) 2019 Minio, Inc.
|
* Minio Cloud Storage, (C) 2019 Minio, Inc.
|
||||||
@ -18,11 +19,11 @@
|
|||||||
|
|
||||||
package sha256
|
package sha256
|
||||||
|
|
||||||
func blockShaGo(dig *digest, p []byte) {
|
func blockIntelShaGo(dig *digest, p []byte) {
|
||||||
panic("blockShaGo called unexpectedly")
|
panic("blockIntelShaGo called unexpectedly")
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
func blockArmGo(dig *digest, p []byte) {
|
func blockArmSha2Go(dig *digest, p []byte) {
|
||||||
panic("blockArmGo called unexpectedly")
|
panic("blockArmSha2Go called unexpectedly")
|
||||||
}
|
}
|
||||||
|
|||||||
8
vendor/modules.txt
vendored
8
vendor/modules.txt
vendored
@ -299,8 +299,8 @@ github.com/klauspost/compress/internal/cpuinfo
|
|||||||
github.com/klauspost/compress/internal/snapref
|
github.com/klauspost/compress/internal/snapref
|
||||||
github.com/klauspost/compress/zstd
|
github.com/klauspost/compress/zstd
|
||||||
github.com/klauspost/compress/zstd/internal/xxhash
|
github.com/klauspost/compress/zstd/internal/xxhash
|
||||||
# github.com/klauspost/cpuid/v2 v2.0.4
|
# github.com/klauspost/cpuid/v2 v2.2.5
|
||||||
## explicit; go 1.13
|
## explicit; go 1.15
|
||||||
github.com/klauspost/cpuid/v2
|
github.com/klauspost/cpuid/v2
|
||||||
# github.com/matttproud/golang_protobuf_extensions v1.0.4
|
# github.com/matttproud/golang_protobuf_extensions v1.0.4
|
||||||
## explicit; go 1.9
|
## explicit; go 1.9
|
||||||
@ -308,8 +308,8 @@ github.com/matttproud/golang_protobuf_extensions/pbutil
|
|||||||
# github.com/miekg/pkcs11 v1.1.1
|
# github.com/miekg/pkcs11 v1.1.1
|
||||||
## explicit; go 1.12
|
## explicit; go 1.12
|
||||||
github.com/miekg/pkcs11
|
github.com/miekg/pkcs11
|
||||||
# github.com/minio/sha256-simd v1.0.0
|
# github.com/minio/sha256-simd v1.0.1
|
||||||
## explicit; go 1.13
|
## explicit; go 1.17
|
||||||
github.com/minio/sha256-simd
|
github.com/minio/sha256-simd
|
||||||
# github.com/mistifyio/go-zfs/v3 v3.0.1
|
# github.com/mistifyio/go-zfs/v3 v3.0.1
|
||||||
## explicit; go 1.14
|
## explicit; go 1.14
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user