8b5cc2e1dc
full diff: https://github.com/containerd/consolve/compare/v1.0.0...v1.0.1
vendor golang.org/x/sys 2334cc1a136f0a5b4384f1a27e3634457be08553
full diff: ed371f2e16...2334cc1a13
- unix: add Darwin support for clonefile syscalls
- Adds openat2 for linux
openat2 is a new syscall added to Linux 5.6. It provides a superset of
openat(2) functionality, extending it with flags telling the kernel how
to resolve the paths.
For more info, see https://lwn.net/Articles/803237/
NOTE that this is a second attempt to add the call; the previous one
(https://golang.org/cl/227280) was reverted
(https://golang.org/cl/227846) due to the test case failure on ARM
(https://golang.org/issue/38357).
This CL has the test case reworked to be less assumptive to the testing
environment. In particular, it first tries if the most simplistic
openat2() call succeeds, and skips the test otherwise. It is done that
way because CI can be under under different kernels and in various
envrionments -- in particular, Docker+seccomp can result in EPERM from a
system call (which is not expected otherwise).
For previous discussions about the test case, see
https://golang.org/cl/227865.
Signed-off-by: Sebastiaan van Stijn <github@gone.nl>
268 lines
9.9 KiB
Go
268 lines
9.9 KiB
Go
// Copyright 2018 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package cpu implements processor feature detection for
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// various CPU architectures.
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package cpu
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import (
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"os"
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"strings"
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)
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// Initialized reports whether the CPU features were initialized.
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//
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// For some GOOS/GOARCH combinations initialization of the CPU features depends
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// on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
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// Initialized will report false if reading the file fails.
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var Initialized bool
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// CacheLinePad is used to pad structs to avoid false sharing.
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type CacheLinePad struct{ _ [cacheLineSize]byte }
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// X86 contains the supported CPU features of the
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// current X86/AMD64 platform. If the current platform
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// is not X86/AMD64 then all feature flags are false.
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//
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// X86 is padded to avoid false sharing. Further the HasAVX
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// and HasAVX2 are only set if the OS supports XMM and YMM
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// registers in addition to the CPUID feature bit being set.
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var X86 struct {
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasRDRAND bool // RDRAND instruction (on-chip random number generator)
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HasRDSEED bool // RDSEED instruction (on-chip random number generator)
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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}
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// ARM64 contains the supported CPU features of the
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// current ARMv8(aarch64) platform. If the current platform
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// is not arm64 then all feature flags are false.
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var ARM64 struct {
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_ CacheLinePad
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HasFP bool // Floating-point instruction set (always available)
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HasASIMD bool // Advanced SIMD (always available)
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HasEVTSTRM bool // Event stream support
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HasAES bool // AES hardware implementation
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HasPMULL bool // Polynomial multiplication instruction set
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HasSHA1 bool // SHA1 hardware implementation
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HasSHA2 bool // SHA2 hardware implementation
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HasCRC32 bool // CRC32 hardware implementation
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HasATOMICS bool // Atomic memory operation instruction set
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HasFPHP bool // Half precision floating-point instruction set
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HasASIMDHP bool // Advanced SIMD half precision instruction set
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HasCPUID bool // CPUID identification scheme registers
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HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
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HasJSCVT bool // Javascript conversion from floating-point to integer
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HasFCMA bool // Floating-point multiplication and addition of complex numbers
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HasLRCPC bool // Release Consistent processor consistent support
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HasDCPOP bool // Persistent memory support
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HasSHA3 bool // SHA3 hardware implementation
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HasSM3 bool // SM3 hardware implementation
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HasSM4 bool // SM4 hardware implementation
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HasASIMDDP bool // Advanced SIMD double precision instruction set
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HasSHA512 bool // SHA512 hardware implementation
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HasSVE bool // Scalable Vector Extensions
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HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
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_ CacheLinePad
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}
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// ARM contains the supported CPU features of the current ARM (32-bit) platform.
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// All feature flags are false if:
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// 1. the current platform is not arm, or
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// 2. the current operating system is not Linux.
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var ARM struct {
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_ CacheLinePad
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HasSWP bool // SWP instruction support
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HasHALF bool // Half-word load and store support
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HasTHUMB bool // ARM Thumb instruction set
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Has26BIT bool // Address space limited to 26-bits
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HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support
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HasFPA bool // Floating point arithmetic support
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HasVFP bool // Vector floating point support
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HasEDSP bool // DSP Extensions support
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HasJAVA bool // Java instruction set
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HasIWMMXT bool // Intel Wireless MMX technology support
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HasCRUNCH bool // MaverickCrunch context switching and handling
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HasTHUMBEE bool // Thumb EE instruction set
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HasNEON bool // NEON instruction set
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HasVFPv3 bool // Vector floating point version 3 support
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HasVFPv3D16 bool // Vector floating point version 3 D8-D15
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HasTLS bool // Thread local storage support
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HasVFPv4 bool // Vector floating point version 4 support
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HasIDIVA bool // Integer divide instruction support in ARM mode
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HasIDIVT bool // Integer divide instruction support in Thumb mode
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HasVFPD32 bool // Vector floating point version 3 D15-D31
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HasLPAE bool // Large Physical Address Extensions
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HasEVTSTRM bool // Event stream support
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HasAES bool // AES hardware implementation
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HasPMULL bool // Polynomial multiplication instruction set
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HasSHA1 bool // SHA1 hardware implementation
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HasSHA2 bool // SHA2 hardware implementation
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HasCRC32 bool // CRC32 hardware implementation
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_ CacheLinePad
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}
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// MIPS64X contains the supported CPU features of the current mips64/mips64le
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// platforms. If the current platform is not mips64/mips64le or the current
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// operating system is not Linux then all feature flags are false.
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var MIPS64X struct {
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_ CacheLinePad
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HasMSA bool // MIPS SIMD architecture
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_ CacheLinePad
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}
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// PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
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// If the current platform is not ppc64/ppc64le then all feature flags are false.
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//
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// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
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// since there are no optional categories. There are some exceptions that also
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// require kernel support to work (DARN, SCV), so there are feature bits for
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// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
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// The struct is padded to avoid false sharing.
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var PPC64 struct {
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_ CacheLinePad
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HasDARN bool // Hardware random number generator (requires kernel enablement)
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HasSCV bool // Syscall vectored (requires kernel enablement)
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IsPOWER8 bool // ISA v2.07 (POWER8)
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IsPOWER9 bool // ISA v3.00 (POWER9)
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_ CacheLinePad
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}
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// S390X contains the supported CPU features of the current IBM Z
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// (s390x) platform. If the current platform is not IBM Z then all
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// feature flags are false.
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//
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// S390X is padded to avoid false sharing. Further HasVX is only set
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// if the OS supports vector registers in addition to the STFLE
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// feature bit being set.
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var S390X struct {
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_ CacheLinePad
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HasZARCH bool // z/Architecture mode is active [mandatory]
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HasSTFLE bool // store facility list extended
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HasLDISP bool // long (20-bit) displacements
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HasEIMM bool // 32-bit immediates
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HasDFP bool // decimal floating point
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HasETF3EH bool // ETF-3 enhanced
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HasMSA bool // message security assist (CPACF)
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HasAES bool // KM-AES{128,192,256} functions
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HasAESCBC bool // KMC-AES{128,192,256} functions
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HasAESCTR bool // KMCTR-AES{128,192,256} functions
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HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
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HasGHASH bool // KIMD-GHASH function
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HasSHA1 bool // K{I,L}MD-SHA-1 functions
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HasSHA256 bool // K{I,L}MD-SHA-256 functions
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HasSHA512 bool // K{I,L}MD-SHA-512 functions
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HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
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HasVX bool // vector facility
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HasVXE bool // vector-enhancements facility 1
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_ CacheLinePad
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}
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func init() {
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archInit()
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initOptions()
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processOptions()
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}
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// options contains the cpu debug options that can be used in GODEBUG.
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// Options are arch dependent and are added by the arch specific initOptions functions.
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// Features that are mandatory for the specific GOARCH should have the Required field set
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// (e.g. SSE2 on amd64).
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var options []option
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// Option names should be lower case. e.g. avx instead of AVX.
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type option struct {
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Name string
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Feature *bool
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Specified bool // whether feature value was specified in GODEBUG
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Enable bool // whether feature should be enabled
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Required bool // whether feature is mandatory and can not be disabled
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}
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func processOptions() {
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env := os.Getenv("GODEBUG")
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field:
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for env != "" {
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field := ""
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i := strings.IndexByte(env, ',')
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if i < 0 {
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field, env = env, ""
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} else {
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field, env = env[:i], env[i+1:]
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}
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if len(field) < 4 || field[:4] != "cpu." {
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continue
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}
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i = strings.IndexByte(field, '=')
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if i < 0 {
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print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n")
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continue
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}
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key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on"
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var enable bool
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switch value {
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case "on":
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enable = true
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case "off":
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enable = false
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default:
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print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n")
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continue field
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}
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if key == "all" {
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for i := range options {
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options[i].Specified = true
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options[i].Enable = enable || options[i].Required
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}
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continue field
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}
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for i := range options {
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if options[i].Name == key {
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options[i].Specified = true
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options[i].Enable = enable
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continue field
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}
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}
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print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n")
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}
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for _, o := range options {
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if !o.Specified {
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continue
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}
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if o.Enable && !*o.Feature {
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print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n")
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continue
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}
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if !o.Enable && o.Required {
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print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n")
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continue
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}
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*o.Feature = o.Enable
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}
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}
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