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Change sequential request detection logic

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Changing sequential request detection so that a miss request is
recognized as sequential after needed cachelines are evicted
and mapped to the request in a sequential order.

Signed-off-by: Adam Rutkowski <adam.j.rutkowski@intel.com>
This commit is contained in:
Adam Rutkowski
2021-03-05 11:20:46 +01:00
parent 056217d103
commit 3bd0f6b6c4
3 changed files with 77 additions and 43 deletions
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5
src/ocf_request.h
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@@ -18,6 +18,8 @@ struct ocf_req_info {
unsigned int hit_no;
unsigned int invalid_no;
unsigned int re_part_no;
unsigned int seq_no;
unsigned int insert_no;
uint32_t dirty_all;
/*!< Number of dirty line in request*/
@@ -25,9 +27,6 @@ struct ocf_req_info {
uint32_t dirty_any;
/*!< Indicates that at least one request is dirty */
uint32_t seq_req : 1;
/*!< Sequential cache request flag. */
uint32_t flush_metadata : 1;
/*!< This bit tells if metadata flushing is required */