Allocator structures cacheline alignment
Align atomic fields to a different cacheline, so no false sharing between CPUs occur. Signed-off-by: Kozlowski Mateusz <mateusz.kozlowski@intel.com>
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@ -14,16 +14,16 @@ struct _env_allocator {
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/*!< Memory pool ID unique name */
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char *name;
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/*!< Size of specific item of memory pool */
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uint32_t item_size;
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/*!< OS handle to memory pool */
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struct kmem_cache *kmem_cache;
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/*!< Number of currently allocated items in pool */
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atomic_t count;
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struct cas_reserve_pool *rpool;
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/*!< Size of specific item of memory pool */
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uint32_t item_size;
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/*!< Number of currently allocated items in pool */
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atomic_t count __attribute__((aligned(64)));
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};
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static inline size_t env_allocator_align(size_t size)
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@ -25,11 +25,17 @@
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#define CAS_DEBUG_PARAM(format, ...)
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#endif
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/* This is currently 24B padded/force aligned to 32B.
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* With a 64B cacheline this means two structs on different cores may
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* invalidate each other. This shouldn't happen between different physical
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* CPUs and cause false sharing though, since with an even number of cores
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* per CPU same cacheline shouldn't be polluted from the other physical CPU.
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* */
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struct _cas_reserve_pool_per_cpu {
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spinlock_t lock;
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struct list_head list;
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atomic_t count;
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};
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} __attribute__((__aligned__(32)));
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struct cas_reserve_pool {
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uint32_t limit;
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