From 1379abb94b6432e4104d56b59b3ef104de1e9ff3 Mon Sep 17 00:00:00 2001
From: Sebastien Boeuf <sebastien.boeuf@intel.com>
Date: Tue, 26 Nov 2019 14:50:53 -0800
Subject: [PATCH] pci: msi: Fix MSG_CTL update through 32 bits write

If the MSG_CTL is being written from a 32 bits write access, the offset
won't be 0x2, but 0x0 instead. That's simply because 32 bits access have
to be aligned on each double word.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
 pci/src/msi.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pci/src/msi.rs b/pci/src/msi.rs
index aa553edd9..33cce4d99 100644
--- a/pci/src/msi.rs
+++ b/pci/src/msi.rs
@@ -132,7 +132,7 @@ impl MsiCap {
             4 => {
                 let value = LittleEndian::read_u32(data);
                 match offset {
-                    MSI_MSG_CTL_OFFSET => {
+                    0x0 => {
                         self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
                             | ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
                     }