From 14c0e8424b203e3342e3b41838eba1424df971b2 Mon Sep 17 00:00:00 2001 From: Michael Zhao Date: Wed, 16 Jun 2021 15:31:55 +0800 Subject: [PATCH] aarch64: Fix wrong MPIDR setting Fixed wrong MPIDR value setting for VCPUs in FDT. The wrong setting made only 16 VCPUs can be enabled at most, all other VCPUs were showing off-line. The issue was introduced when we were migrating FDT-generating code to vmm-fdt crate. Signed-off-by: Michael Zhao --- arch/src/aarch64/fdt.rs | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/src/aarch64/fdt.rs b/arch/src/aarch64/fdt.rs index 81e1a6e8c..ba8c7c39d 100644 --- a/arch/src/aarch64/fdt.rs +++ b/arch/src/aarch64/fdt.rs @@ -130,7 +130,7 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult< fdt.property_u32("#size-cells", 0x0)?; let num_cpus = vcpu_mpidr.len(); - for cpu_id in 0..num_cpus { + for (cpu_id, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) { let cpu_name = format!("cpu@{:x}", cpu_id); let cpu_node = fdt.begin_node(&cpu_name)?; fdt.property_string("device_type", "cpu")?; @@ -139,7 +139,9 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult< // This is required on armv8 64-bit. See aforementioned documentation. fdt.property_string("enable-method", "psci")?; } - fdt.property_u32("reg", cpu_id as u32)?; + // Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register. + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html. + fdt.property_u32("reg", (mpidr & 0x7FFFFF) as u32)?; fdt.end_node(cpu_node)?; } fdt.end_node(cpus_node)?;