mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2026-08-05 02:19:16 +00:00
cloud-hypervisor: Add devices crate
Based on the Firecracker devices crate from commit 9cdb5b2. It is a trimmed down version compared to the Firecracker one, to remove a bunch of pulled dependencies (logger, metrics, rate limiter, etc...). Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Samuel Ortiz
10
devices/src/legacy/mod.rs
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10
devices/src/legacy/mod.rs
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// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the THIRD-PARTY file.
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mod serial;
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pub use self::serial::Serial;
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384
devices/src/legacy/serial.rs
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384
devices/src/legacy/serial.rs
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// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the THIRD-PARTY file.
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use std::collections::VecDeque;
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use std::{io, result};
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use vmm_sys_util::{EventFd, Result};
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use BusDevice;
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const LOOP_SIZE: usize = 0x40;
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const DATA: u8 = 0;
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const IER: u8 = 1;
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const IIR: u8 = 2;
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const LCR: u8 = 3;
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const MCR: u8 = 4;
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const LSR: u8 = 5;
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const MSR: u8 = 6;
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const SCR: u8 = 7;
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const DLAB_LOW: u8 = 0;
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const DLAB_HIGH: u8 = 1;
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const IER_RECV_BIT: u8 = 0x1;
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const IER_THR_BIT: u8 = 0x2;
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const IER_FIFO_BITS: u8 = 0x0f;
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const IIR_FIFO_BITS: u8 = 0xc0;
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const IIR_NONE_BIT: u8 = 0x1;
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const IIR_THR_BIT: u8 = 0x2;
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const IIR_RECV_BIT: u8 = 0x4;
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const LCR_DLAB_BIT: u8 = 0x80;
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const LSR_DATA_BIT: u8 = 0x1;
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const LSR_EMPTY_BIT: u8 = 0x20;
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const LSR_IDLE_BIT: u8 = 0x40;
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const MCR_LOOP_BIT: u8 = 0x10;
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const DEFAULT_INTERRUPT_IDENTIFICATION: u8 = IIR_NONE_BIT; // no pending interrupt
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const DEFAULT_LINE_STATUS: u8 = LSR_EMPTY_BIT | LSR_IDLE_BIT; // THR empty and line is idle
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const DEFAULT_LINE_CONTROL: u8 = 0x3; // 8-bits per character
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const DEFAULT_MODEM_CONTROL: u8 = 0x8; // Auxiliary output 2
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const DEFAULT_MODEM_STATUS: u8 = 0x20 | 0x10 | 0x80; // data ready, clear to send, carrier detect
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const DEFAULT_BAUD_DIVISOR: u16 = 12; // 9600 bps
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/// Emulates serial COM ports commonly seen on x86 I/O ports 0x3f8/0x2f8/0x3e8/0x2e8.
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///
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/// This can optionally write the guest's output to a Write trait object. To send input to the
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/// guest, use `queue_input_bytes`.
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pub struct Serial {
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interrupt_enable: u8,
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interrupt_identification: u8,
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interrupt_evt: EventFd,
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line_control: u8,
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line_status: u8,
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modem_control: u8,
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modem_status: u8,
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scratch: u8,
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baud_divisor: u16,
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in_buffer: VecDeque<u8>,
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out: Option<Box<io::Write + Send>>,
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}
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impl Serial {
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fn new(interrupt_evt: EventFd, out: Option<Box<io::Write + Send>>) -> Serial {
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Serial {
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interrupt_enable: 0,
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interrupt_identification: DEFAULT_INTERRUPT_IDENTIFICATION,
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interrupt_evt,
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line_control: DEFAULT_LINE_CONTROL,
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line_status: DEFAULT_LINE_STATUS,
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modem_control: DEFAULT_MODEM_CONTROL,
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modem_status: DEFAULT_MODEM_STATUS,
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scratch: 0,
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baud_divisor: DEFAULT_BAUD_DIVISOR,
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in_buffer: VecDeque::new(),
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out,
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}
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}
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/// Constructs a Serial port ready for output.
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pub fn new_out(interrupt_evt: EventFd, out: Box<io::Write + Send>) -> Serial {
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Self::new(interrupt_evt, Some(out))
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}
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/// Constructs a Serial port with no connected output.
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pub fn new_sink(interrupt_evt: EventFd) -> Serial {
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Self::new(interrupt_evt, None)
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}
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/// Queues raw bytes for the guest to read and signals the interrupt if the line status would
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/// change.
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pub fn queue_input_bytes(&mut self, c: &[u8]) -> Result<()> {
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if !self.is_loop() {
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self.in_buffer.extend(c);
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self.recv_data()?;
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}
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Ok(())
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}
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fn is_dlab_set(&self) -> bool {
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(self.line_control & LCR_DLAB_BIT) != 0
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}
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fn is_recv_intr_enabled(&self) -> bool {
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(self.interrupt_enable & IER_RECV_BIT) != 0
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}
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fn is_thr_intr_enabled(&self) -> bool {
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(self.interrupt_enable & IER_THR_BIT) != 0
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}
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fn is_loop(&self) -> bool {
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(self.modem_control & MCR_LOOP_BIT) != 0
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}
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fn add_intr_bit(&mut self, bit: u8) {
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self.interrupt_identification &= !IIR_NONE_BIT;
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self.interrupt_identification |= bit;
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}
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fn del_intr_bit(&mut self, bit: u8) {
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self.interrupt_identification &= !bit;
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if self.interrupt_identification == 0x0 {
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self.interrupt_identification = IIR_NONE_BIT;
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}
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}
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fn thr_empty(&mut self) -> Result<()> {
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if self.is_thr_intr_enabled() {
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self.add_intr_bit(IIR_THR_BIT);
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self.trigger_interrupt()?
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}
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Ok(())
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}
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fn recv_data(&mut self) -> Result<()> {
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if self.is_recv_intr_enabled() {
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self.add_intr_bit(IIR_RECV_BIT);
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self.trigger_interrupt()?
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}
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self.line_status |= LSR_DATA_BIT;
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Ok(())
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}
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fn trigger_interrupt(&mut self) -> result::Result<(), io::Error> {
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self.interrupt_evt.write(1)
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}
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fn iir_reset(&mut self) {
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self.interrupt_identification = DEFAULT_INTERRUPT_IDENTIFICATION;
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}
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fn handle_write(&mut self, offset: u8, v: u8) -> Result<()> {
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match offset as u8 {
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DLAB_LOW if self.is_dlab_set() => {
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self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(v)
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}
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DLAB_HIGH if self.is_dlab_set() => {
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self.baud_divisor = (self.baud_divisor & 0x00ff) | ((u16::from(v)) << 8)
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}
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DATA => {
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if self.is_loop() {
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if self.in_buffer.len() < LOOP_SIZE {
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self.in_buffer.push_back(v);
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self.recv_data()?;
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}
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} else {
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if let Some(out) = self.out.as_mut() {
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out.write_all(&[v])?;
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out.flush()?;
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}
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self.thr_empty()?;
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}
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}
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IER => self.interrupt_enable = v & IER_FIFO_BITS,
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LCR => self.line_control = v,
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MCR => self.modem_control = v,
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SCR => self.scratch = v,
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_ => {}
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}
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Ok(())
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}
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}
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impl BusDevice for Serial {
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fn read(&mut self, offset: u64, data: &mut [u8]) {
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if data.len() != 1 {
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return;
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}
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data[0] = match offset as u8 {
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DLAB_LOW if self.is_dlab_set() => self.baud_divisor as u8,
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DLAB_HIGH if self.is_dlab_set() => (self.baud_divisor >> 8) as u8,
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DATA => {
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self.del_intr_bit(IIR_RECV_BIT);
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if self.in_buffer.len() <= 1 {
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self.line_status &= !LSR_DATA_BIT;
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}
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self.in_buffer.pop_front().unwrap_or_default()
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}
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IER => self.interrupt_enable,
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IIR => {
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let v = self.interrupt_identification | IIR_FIFO_BITS;
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self.iir_reset();
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v
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}
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LCR => self.line_control,
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MCR => self.modem_control,
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LSR => self.line_status,
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MSR => self.modem_status,
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SCR => self.scratch,
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_ => 0,
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};
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}
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fn write(&mut self, offset: u64, data: &[u8]) {
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if data.len() != 1 {
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return;
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}
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if let Err(_e) = self.handle_write(offset as u8, data[0]) {}
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use std::io;
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use std::sync::{Arc, Mutex};
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#[derive(Clone)]
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struct SharedBuffer {
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buf: Arc<Mutex<Vec<u8>>>,
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}
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impl SharedBuffer {
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fn new() -> SharedBuffer {
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SharedBuffer {
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buf: Arc::new(Mutex::new(Vec::new())),
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}
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}
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}
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impl io::Write for SharedBuffer {
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fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
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self.buf.lock().unwrap().write(buf)
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}
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fn flush(&mut self) -> io::Result<()> {
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self.buf.lock().unwrap().flush()
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}
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}
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#[test]
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fn serial_output() {
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let intr_evt = EventFd::new().unwrap();
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let serial_out = SharedBuffer::new();
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let mut serial = Serial::new_out(intr_evt, Box::new(serial_out.clone()));
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serial.write(DATA as u64, &['x' as u8, 'y' as u8]);
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serial.write(DATA as u64, &['a' as u8]);
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serial.write(DATA as u64, &['b' as u8]);
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serial.write(DATA as u64, &['c' as u8]);
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assert_eq!(
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serial_out.buf.lock().unwrap().as_slice(),
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&['a' as u8, 'b' as u8, 'c' as u8]
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);
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}
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#[test]
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fn serial_input() {
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let intr_evt = EventFd::new().unwrap();
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let serial_out = SharedBuffer::new();
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let mut serial =
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Serial::new_out(intr_evt.try_clone().unwrap(), Box::new(serial_out.clone()));
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// write 1 to the interrupt event fd, so that read doesn't block in case the event fd
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// counter doesn't change (for 0 it blocks)
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assert!(intr_evt.write(1).is_ok());
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serial.write(IER as u64, &[IER_RECV_BIT]);
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serial
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.queue_input_bytes(&['a' as u8, 'b' as u8, 'c' as u8])
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.unwrap();
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assert_eq!(intr_evt.read().unwrap(), 2);
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// check if reading in a 2-length array doesn't have side effects
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let mut data = [0u8, 0u8];
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data, [0u8, 0u8]);
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let mut data = [0u8];
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serial.read(LSR as u64, &mut data[..]);
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assert_ne!(data[0] & LSR_DATA_BIT, 0);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'a' as u8);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'b' as u8);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'c' as u8);
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// check if reading from the largest u8 offset returns 0
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serial.read(0xff, &mut data[..]);
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assert_eq!(data[0], 0);
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}
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#[test]
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fn serial_thr() {
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let intr_evt = EventFd::new().unwrap();
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let mut serial = Serial::new_sink(intr_evt.try_clone().unwrap());
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// write 1 to the interrupt event fd, so that read doesn't block in case the event fd
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// counter doesn't change (for 0 it blocks)
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assert!(intr_evt.write(1).is_ok());
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serial.write(IER as u64, &[IER_THR_BIT]);
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serial.write(DATA as u64, &['a' as u8]);
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assert_eq!(intr_evt.read().unwrap(), 2);
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let mut data = [0u8];
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serial.read(IER as u64, &mut data[..]);
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assert_eq!(data[0] & IER_FIFO_BITS, IER_THR_BIT);
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serial.read(IIR as u64, &mut data[..]);
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assert_ne!(data[0] & IIR_THR_BIT, 0);
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}
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#[test]
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fn serial_dlab() {
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let mut serial = Serial::new_sink(EventFd::new().unwrap());
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serial.write(LCR as u64, &[LCR_DLAB_BIT as u8]);
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serial.write(DLAB_LOW as u64, &[0x12 as u8]);
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serial.write(DLAB_HIGH as u64, &[0x34 as u8]);
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let mut data = [0u8];
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serial.read(LCR as u64, &mut data[..]);
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assert_eq!(data[0], LCR_DLAB_BIT as u8);
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serial.read(DLAB_LOW as u64, &mut data[..]);
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assert_eq!(data[0], 0x12);
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serial.read(DLAB_HIGH as u64, &mut data[..]);
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assert_eq!(data[0], 0x34);
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}
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#[test]
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fn serial_modem() {
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let mut serial = Serial::new_sink(EventFd::new().unwrap());
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serial.write(MCR as u64, &[MCR_LOOP_BIT as u8]);
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serial.write(DATA as u64, &['a' as u8]);
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serial.write(DATA as u64, &['b' as u8]);
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serial.write(DATA as u64, &['c' as u8]);
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let mut data = [0u8];
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serial.read(MSR as u64, &mut data[..]);
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assert_eq!(data[0], DEFAULT_MODEM_STATUS as u8);
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serial.read(MCR as u64, &mut data[..]);
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assert_eq!(data[0], MCR_LOOP_BIT as u8);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'a' as u8);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'b' as u8);
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serial.read(DATA as u64, &mut data[..]);
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assert_eq!(data[0], 'c' as u8);
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}
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#[test]
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fn serial_scratch() {
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let mut serial = Serial::new_sink(EventFd::new().unwrap());
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serial.write(SCR as u64, &[0x12 as u8]);
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let mut data = [0u8];
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serial.read(SCR as u64, &mut data[..]);
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assert_eq!(data[0], 0x12 as u8);
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}
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}
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