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hypervisor: cpu: Expand Set/GetCoreRegisters variant

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Since RISC-V has its own definition of `CoreRegister`, expand the Aarch
variant to avoid collision of `HypervisorCpuError`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
This commit is contained in:
Ruoqing He
2024-09-23 12:14:34 +08:00
committed by Rob Bradford
parent e9f137dc4a
commit 2668dbbd8b
2 changed files with 27 additions and 27 deletions
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8
hypervisor/src/cpu.rs
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@@ -209,13 +209,13 @@ pub enum HypervisorCpuError {
///
/// Getting AArch64 core register error
///
#[error("Failed to get core register: {0}")]
GetCoreRegister(#[source] anyhow::Error),
#[error("Failed to get aarch64 core register: {0}")]
GetAarchCoreRegister(#[source] anyhow::Error),
///
/// Setting AArch64 core register error
///
#[error("Failed to set core register: {0}")]
SetCoreRegister(#[source] anyhow::Error),
#[error("Failed to set aarch64 core register: {0}")]
SetAarchCoreRegister(#[source] anyhow::Error),
///
/// Getting AArch64 registers list error
///