From 28aa81e66bf93ad8df77712eb113d73e55e7e352 Mon Sep 17 00:00:00 2001 From: Anatol Belski Date: Sat, 23 May 2026 16:09:39 +0200 Subject: [PATCH] virtio-devices: Test PCI CFG access length clamping Verify that bar_access_params clamps the access length to cap.length when the PCI config read buffer is larger. Signed-off-by: Anatol Belski --- virtio-devices/src/transport/pci_device.rs | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/virtio-devices/src/transport/pci_device.rs b/virtio-devices/src/transport/pci_device.rs index 3923eb226..5c9377044 100644 --- a/virtio-devices/src/transport/pci_device.rs +++ b/virtio-devices/src/transport/pci_device.rs @@ -1486,4 +1486,19 @@ mod unit_tests { (size_of::() as u8) + VIRTIO_PCI_CAP_LEN_OFFSET ); } + + #[test] + fn bar_access_params_clamps_to_cap_length() { + let mut cap = VirtioPciCfgCap::new(); + let slice = cap.as_mut_slice(); + + // Program cap.offset = 0x14, cap.length = 1 (byte access) + slice[6..10].copy_from_slice(&0x14u32.to_le_bytes()); + slice[10..14].copy_from_slice(&1u32.to_le_bytes()); + + // PCI config reads always produce 4 bytes, but cap.length = 1 + let (bar_offset, access_len) = cap.bar_access_params(4); + assert_eq!(bar_offset, 0x14); + assert_eq!(access_len, 1); + } }