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misc: Eliminate use of assert!((...).is_ok())

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Asserting on .is_ok()/.is_err() leads to hard to debug failures (as if
the test fails, it will only say "assertion failed: false". We replace
these with `.unwrap()`, which also prints the exact error variant that
was unexpectedly encountered (we can to this these days thanks to
efforts to implement Display and Debug for our error types). If the
assert!((...).is_ok()) was followed by an .unwrap() anyway, we just drop
the assert.

Inspired by and quoted from @roypat.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
This commit is contained in:
Ruoqing He
2024-09-30 19:07:39 +00:00
committed by Rob Bradford
parent 83bcf2a1ff
commit 297236a7c0
25 changed files with 244 additions and 281 deletions
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12
hypervisor/src/arch/x86/emulator/instructions/cmp.rs
View File

@@ -220,7 +220,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x38, 0xc4]; // cmp ah,al
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
assert_eq!(0b1000100, rflags);
@@ -234,7 +234,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x83, 0xf8, 0x64]; // cmp eax,100
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
assert_eq!(0b100, rflags);
@@ -248,7 +248,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x83, 0xf8, 0xff]; // cmp eax,-1
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
assert_eq!(0b101, rflags);
@@ -263,7 +263,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x48, 0x39, 0xd8, 0x00, 0xc3]; // cmp rax,rbx + two bytes garbage
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax), (Register::RBX, rbx)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
assert_eq!(0b100, rflags);
@@ -290,7 +290,7 @@ mod tests {
vec![(Register::RAX, rax), (Register::RBX, rbx)],
None,
);
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(0).unwrap().flags() & FLAGS_MASK;
assert_eq!(d.2, rflags);
@@ -318,7 +318,7 @@ mod tests {
vec![(Register::RAX, rax), (Register::RBX, rbx)],
None,
);
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
let rflags: u64 = vmm.cpu_state(0).unwrap().flags() & FLAGS_MASK;
assert_eq!(d.2, rflags);

38
hypervisor/src/arch/x86/emulator/instructions/mov.rs
View File

@@ -280,7 +280,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x48, 0x89, 0xd8];
let mut vmm = MockVmm::new(ip, vec![(Register::RBX, rbx)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rax: u64 = vmm
.cpu_state(cpu_id)
@@ -298,7 +298,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x48, 0xb8, 0x44, 0x33, 0x22, 0x11, 0x44, 0x33, 0x22, 0x11];
let mut vmm = MockVmm::new(ip, vec![], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rax: u64 = vmm
.cpu_state(cpu_id)
@@ -318,7 +318,7 @@ mod tests {
let memory: [u8; 8] = target_rax.to_le_bytes();
let insn = [0x48, 0x8b, 0x04, 0x00];
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], Some((rax + rax, &memory)));
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
rax = vmm
.cpu_state(cpu_id)
@@ -336,7 +336,7 @@ mod tests {
let cpu_id = 0;
let insn = [0xb0, 0x11];
let mut vmm = MockVmm::new(ip, vec![], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let al = vmm
.cpu_state(cpu_id)
@@ -354,7 +354,7 @@ mod tests {
let cpu_id = 0;
let insn = [0xb8, 0x11, 0x00, 0x00, 0x00];
let mut vmm = MockVmm::new(ip, vec![], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let eax = vmm
.cpu_state(cpu_id)
@@ -372,7 +372,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x48, 0xc7, 0xc0, 0x44, 0x33, 0x22, 0x11];
let mut vmm = MockVmm::new(ip, vec![], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let rax: u64 = vmm
.cpu_state(cpu_id)
@@ -395,7 +395,7 @@ mod tests {
vec![(Register::RAX, rax), (Register::DH, dh.into())],
None,
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let mut memory: [u8; 1] = [0; 1];
vmm.read_memory(rax, &mut memory).unwrap();
@@ -416,7 +416,7 @@ mod tests {
vec![(Register::RAX, rax), (Register::ESI, esi.into())],
None,
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let mut memory: [u8; 4] = [0; 4];
vmm.read_memory(rax, &mut memory).unwrap();
@@ -438,7 +438,7 @@ mod tests {
vec![(Register::RAX, rax), (Register::EDI, edi.into())],
None,
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let mut memory: [u8; 4] = [0; 4];
vmm.read_memory(rax + displacement, &mut memory).unwrap();
@@ -461,7 +461,7 @@ mod tests {
vec![(Register::RAX, rax)],
Some((rax + displacement, &memory)),
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let new_eax = vmm
.cpu_state(cpu_id)
@@ -486,7 +486,7 @@ mod tests {
vec![(Register::RAX, rax)],
Some((rax + displacement, &memory)),
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let new_al = vmm
.cpu_state(cpu_id)
@@ -511,7 +511,7 @@ mod tests {
0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
];
let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
vmm.emulate_insn(cpu_id, &insn, Some(2)).unwrap();
let rbx: u64 = vmm
.cpu_state(cpu_id)
@@ -538,7 +538,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
// Only run the first instruction.
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
assert_eq!(ip + 7, vmm.cpu_state(cpu_id).unwrap().ip());
@@ -569,7 +569,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
// Run the 2 first instructions.
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
vmm.emulate_insn(cpu_id, &insn, Some(2)).unwrap();
assert_eq!(ip + 7 + 4, vmm.cpu_state(cpu_id).unwrap().ip());
@@ -597,7 +597,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x0f, 0xb6, 0xc3];
let mut vmm = MockVmm::new(ip, vec![(Register::BX, bx as u64)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let eax: u64 = vmm
.cpu_state(cpu_id)
@@ -615,7 +615,7 @@ mod tests {
let cpu_id = 0;
let insn = [0x0f, 0xb6, 0xc7];
let mut vmm = MockVmm::new(ip, vec![(Register::BX, bx as u64)], None);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let eax: u64 = vmm
.cpu_state(cpu_id)
@@ -635,7 +635,7 @@ mod tests {
let insn = [0x0f, 0xb7, 0x03];
let memory: [u8; 1] = value.to_le_bytes();
let mut vmm = MockVmm::new(ip, vec![(Register::RBX, rbx)], Some((rbx, &memory)));
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let eax: u64 = vmm
.cpu_state(cpu_id)
@@ -680,7 +680,7 @@ mod tests {
let memory: [u8; 8] = mem_value.to_le_bytes();
let mut vmm = MockVmm::new(ip, vec![], Some((mem_addr, &memory)));
assert!(vmm.emulate_first_insn(cpu_id, &instruction_bytes).is_ok());
vmm.emulate_first_insn(cpu_id, &instruction_bytes).unwrap();
let ax: u64 = vmm.cpu_state(cpu_id).unwrap().read_reg(register).unwrap();
@@ -737,7 +737,7 @@ mod tests {
]);
let mut vmm = MockVmm::new(ip, vec![(Register::RAX, ax)], None);
assert!(vmm.emulate_first_insn(cpu_id, &instruction_bytes).is_ok());
vmm.emulate_first_insn(cpu_id, &instruction_bytes).unwrap();
match register {
Register::AX => {

14
hypervisor/src/arch/x86/emulator/instructions/movs.rs
View File

@@ -131,7 +131,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x10, &mut data).unwrap();
assert_eq!(0xaabbccdd12345678, <u64>::from_le_bytes(data));
@@ -159,7 +159,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0xc, &mut data).unwrap();
assert_eq!(0x12345678, <u32>::from_le_bytes(data));
@@ -184,7 +184,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x8, &mut data).unwrap();
assert_eq!(0x12345678, <u32>::from_le_bytes(data));
@@ -212,7 +212,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0xc, &mut data).unwrap();
assert_eq!(0x5678, <u16>::from_le_bytes(data));
@@ -243,7 +243,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x8, &mut data).unwrap();
assert_eq!(0x5678, <u16>::from_le_bytes(data));
@@ -269,7 +269,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x8, &mut data).unwrap();
assert_eq!(0x78, data[0]);
@@ -299,7 +299,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x8, &mut data).unwrap();
assert_eq!(0x78, data[0]);

2
hypervisor/src/arch/x86/emulator/instructions/or.rs
View File

@@ -69,7 +69,7 @@ mod tests {
Some((0, &memory)),
);
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
vmm.emulate_first_insn(cpu_id, &insn).unwrap();
let mut out: [u8; 1] = [0; 1];

10
hypervisor/src/arch/x86/emulator/instructions/stos.rs
View File

@@ -112,7 +112,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0, &mut data).unwrap();
assert_eq!(0x12ffffff, <u32>::from_le_bytes(data));
@@ -134,7 +134,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x0, &mut data).unwrap();
assert_eq!(0x12aabb78, <u32>::from_le_bytes(data));
@@ -162,7 +162,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x0, &mut data).unwrap();
assert_eq!(0xaabb5678, <u32>::from_le_bytes(data));
@@ -195,7 +195,7 @@ mod tests {
state.set_flags(state.flags() | DF);
vmm.set_cpu_state(0, state).unwrap();
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x0, &mut data).unwrap();
assert_eq!(0x12345678, <u32>::from_le_bytes(data));
@@ -224,7 +224,7 @@ mod tests {
let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
assert!(vmm.emulate_first_insn(0, &insn).is_ok());
vmm.emulate_first_insn(0, &insn).unwrap();
vmm.read_memory(0x0, &mut data).unwrap();
assert_eq!(0x11223344aabbccdd, <u64>::from_le_bytes(data));

12
hypervisor/src/arch/x86/emulator/mod.rs
View File

@@ -809,7 +809,7 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_insn(cpu_id, &[], Some(2)).is_ok());
vmm.emulate_insn(cpu_id, &[], Some(2)).unwrap();
let rax: u64 = vmm
.cpu_state(cpu_id)
@@ -847,7 +847,7 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_insn(cpu_id, &[], None).is_err());
vmm.emulate_insn(cpu_id, &[], None).unwrap_err();
}
#[test]
@@ -875,7 +875,7 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
vmm.emulate_insn(cpu_id, &insn, Some(2)).unwrap();
let rax: u64 = vmm
.cpu_state(cpu_id)
@@ -910,7 +910,7 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
vmm.emulate_insn(cpu_id, &insn, Some(2)).unwrap();
let rbx: u64 = vmm
.cpu_state(cpu_id)
@@ -945,7 +945,7 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_insn(cpu_id, &insn, Some(1)).is_ok());
vmm.emulate_insn(cpu_id, &insn, Some(1)).unwrap();
let new_ip: u64 = vmm.cpu_state(cpu_id).unwrap().ip();
assert_eq!(new_ip, ip + 0x7 /* length of mov rax,0x1000 */);
@@ -986,6 +986,6 @@ mod tests {
];
let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_err());
vmm.emulate_first_insn(cpu_id, &insn).unwrap_err();
}
}

23
hypervisor/src/kvm/aarch64/gic/mod.rs
View File

@@ -491,7 +491,7 @@ mod tests {
let hv = crate::new().unwrap();
let vm = hv.create_vm().unwrap();
assert!(KvmGicV3Its::new(&*vm, create_test_vgic_config()).is_ok());
KvmGicV3Its::new(&*vm, create_test_vgic_config()).unwrap();
}
#[test]
@@ -501,13 +501,10 @@ mod tests {
let _ = vm.create_vcpu(0, None).unwrap();
let gic = KvmGicV3Its::new(&*vm, create_test_vgic_config()).expect("Cannot create gic");
let res = get_dist_regs(&gic.device);
assert!(res.is_ok());
let state = res.unwrap();
let state = get_dist_regs(&gic.device).unwrap();
assert_eq!(state.len(), 568);
let res = set_dist_regs(&gic.device, &state);
assert!(res.is_ok());
set_dist_regs(&gic.device, &state).unwrap();
}
#[test]
@@ -518,13 +515,11 @@ mod tests {
let gic = KvmGicV3Its::new(&*vm, create_test_vgic_config()).expect("Cannot create gic");
let gicr_typer = vec![123];
let res = get_redist_regs(&gic.device, &gicr_typer);
assert!(res.is_ok());
let state = res.unwrap();
let state = get_redist_regs(&gic.device, &gicr_typer).unwrap();
println!("{}", state.len());
assert!(state.len() == 24);
assert!(set_redist_regs(&gic.device, &gicr_typer, &state).is_ok());
set_redist_regs(&gic.device, &gicr_typer, &state).unwrap();
}
#[test]
@@ -535,13 +530,11 @@ mod tests {
let gic = KvmGicV3Its::new(&*vm, create_test_vgic_config()).expect("Cannot create gic");
let gicr_typer = vec![123];
let res = get_icc_regs(&gic.device, &gicr_typer);
assert!(res.is_ok());
let state = res.unwrap();
let state = get_icc_regs(&gic.device, &gicr_typer).unwrap();
println!("{}", state.len());
assert!(state.len() == 9);
assert!(set_icc_regs(&gic.device, &gicr_typer, &state).is_ok());
set_icc_regs(&gic.device, &gicr_typer, &state).unwrap();
}
#[test]
@@ -553,6 +546,6 @@ mod tests {
.create_vgic(create_test_vgic_config())
.expect("Cannot create gic");
assert!(gic.lock().unwrap().save_data_tables().is_ok());
gic.lock().unwrap().save_data_tables().unwrap();
}
}