pci: Refine pci topology

PciConfigIo is a legacy pci bus dispatcher, which manages all pci
devices including a pci root bridge. However, it is unnecessary to
design a complex hierarchy which redirects every access by PciRoot.

Since pci root bridge is also a pci device instance, and only contains
easy config space read/write, and PciConfigIo actually acts as a pci bus
to dispatch resource based resolving when VMExit, we re-arrange to make
the pci hierarchy clean.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>

pci/src/device.rs

@@ -90,11 +90,11 @@ pub trait PciDevice: BusDevice {
     /// Reads from a BAR region mapped in to the device.
     /// * `addr` - The guest address inside the BAR.
     /// * `data` - Filled with the data from `addr`.
-    fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]);
+    fn read_bar(&mut self, _base: u64, _offset: u64, _data: &mut [u8]) {}
     /// Writes to a BAR region mapped in to the device.
     /// * `addr` - The guest address inside the BAR.
     /// * `data` - The data to write.
-    fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]);
+    fn write_bar(&mut self, _base: u64, _offset: u64, _data: &[u8]) {}
     /// Invoked when the device is sandboxed.
     fn on_device_sandboxed(&mut self) {}
 }