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pci: Refine pci topology

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PciConfigIo is a legacy pci bus dispatcher, which manages all pci
devices including a pci root bridge. However, it is unnecessary to
design a complex hierarchy which redirects every access by PciRoot.

Since pci root bridge is also a pci device instance, and only contains
easy config space read/write, and PciConfigIo actually acts as a pci bus
to dispatch resource based resolving when VMExit, we re-arrange to make
the pci hierarchy clean.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
This commit is contained in:
Jing Liu
2019-06-04 14:51:00 +08:00
committed by Samuel Ortiz
parent 4605ecf1a8
commit 2bb0b22cc1
4 changed files with 125 additions and 130 deletions
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9
pci/src/lib.rs
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@@ -10,20 +10,21 @@ extern crate kvm_ioctls;
extern crate vm_memory;
extern crate vmm_sys_util;
mod bus;
mod configuration;
mod device;
mod msix;
mod root;
pub use self::bus::{PciConfigIo, PciConfigMmio, PciRoot, PciRootError};
pub use self::configuration::{
PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciCapability, PciCapabilityID,
PciClassCode, PciConfiguration, PciHeaderType, PciMassStorageSubclass,
PciNetworkControllerSubclass, PciProgrammingInterface, PciSerialBusSubClass, PciSubclass,
};
pub use self::device::Error as PciDeviceError;
pub use self::device::{InterruptDelivery, InterruptParameters, PciDevice};
pub use self::device::{
Error as PciDeviceError, InterruptDelivery, InterruptParameters, PciDevice,
};
pub use self::msix::{MsixCap, MsixConfig, MsixTableEntry};
pub use self::root::{PciConfigIo, PciConfigMmio, PciRoot, PciRootError};
/// PCI has four interrupt pins A->D.
#[derive(Copy, Clone)]