From 3671f5e94cc07084dceae1930f12b98a1f79c233 Mon Sep 17 00:00:00 2001 From: Rob Bradford Date: Thu, 25 Mar 2021 17:01:21 +0000 Subject: [PATCH] aarch64: Address Rust 1.51.0 clippy issue (redundant_slicing) error: redundant slicing of the whole range Error: --> devices/src/legacy/gpio_pl061.rs:298:37 | 298 | let value = read_le_u32(&data[..]); | ^^^^^^^^^ help: use the original slice instead: `data` | = note: `-D clippy::redundant-slicing` implied by `-D warnings` = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#redundant_slicing Signed-off-by: Rob Bradford --- devices/src/legacy/gpio_pl061.rs | 18 +++++++++--------- devices/src/legacy/rtc_pl031.rs | 16 ++++++++-------- devices/src/legacy/uart_pl011.rs | 8 ++++---- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/devices/src/legacy/gpio_pl061.rs b/devices/src/legacy/gpio_pl061.rs index 843e6c969..253e1d5e2 100644 --- a/devices/src/legacy/gpio_pl061.rs +++ b/devices/src/legacy/gpio_pl061.rs @@ -295,7 +295,7 @@ impl BusDevice for Gpio { fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option> { if data.len() <= 4 { - let value = read_le_u32(&data[..]); + let value = read_le_u32(&data); if let Err(e) = self.handle_write(offset, value) { warn!("Failed to write to GPIO PL061 device: {}", e); } @@ -409,7 +409,7 @@ mod tests { write_le_u32(&mut data, 1); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 1); // Read and write to the GPIODATA register. @@ -418,7 +418,7 @@ mod tests { let offset = 0x00000004 as u64; gpio.write(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 1); // Read and write to the GPIOIS register. @@ -426,7 +426,7 @@ mod tests { write_le_u32(&mut data, 1); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 1); // Read and write to the GPIOIBE register. @@ -434,7 +434,7 @@ mod tests { write_le_u32(&mut data, 2); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 2); // Read and write to the GPIOIEV register. @@ -442,7 +442,7 @@ mod tests { write_le_u32(&mut data, 4); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 4); // Read and write to the GPIOIE register. @@ -451,7 +451,7 @@ mod tests { write_le_u32(&mut data, 7); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 7); let mask = 0x00000002 as u32; @@ -461,7 +461,7 @@ mod tests { // The interrupt line on pin 1 should be on. // Read the GPIOMIS register. gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOMIS, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 2); // Read and Write to the GPIOIC register. @@ -469,7 +469,7 @@ mod tests { write_le_u32(&mut data, 2); gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 2); // Attempts to write beyond the writable space. diff --git a/devices/src/legacy/rtc_pl031.rs b/devices/src/legacy/rtc_pl031.rs index 3632ba65f..2c1e4d6bd 100644 --- a/devices/src/legacy/rtc_pl031.rs +++ b/devices/src/legacy/rtc_pl031.rs @@ -328,7 +328,7 @@ impl BusDevice for Rtc { fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option> { if data.len() <= 4 { - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); if let Err(e) = self.handle_write(offset, v) { warn!("Failed to write to RTC PL031 device: {}", e); } @@ -459,7 +459,7 @@ mod tests { write_le_u32(&mut data, 123); rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 123); // Read and write to the LR register. @@ -471,7 +471,7 @@ mod tests { assert!(rtc.previous_now > previous_now_before); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data); - let v_read = read_le_u32(&data[..]); + let v_read = read_le_u32(&data); assert_eq!((v / NANOS_PER_SECOND) as u32, v_read); // Read and write to IMSC register. @@ -482,14 +482,14 @@ mod tests { // The interrupt line should be on. assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() == 1); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(non_zero & 1, v); // Now test with 0. write_le_u32(&mut data, 0); rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(0, v); // Read and write to the ICR register. @@ -497,10 +497,10 @@ mod tests { rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data); // The interrupt line should be on. assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() > 1); - let v_before = read_le_u32(&data[..]); + let v_before = read_le_u32(&data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); // ICR is a write only register. Data received should stay equal to data sent. assert_eq!(v, v_before); @@ -508,7 +508,7 @@ mod tests { write_le_u32(&mut data, 0); rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data); - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); assert_eq!(v, 1); // Attempts to write beyond the writable space. Using here the space used to read diff --git a/devices/src/legacy/uart_pl011.rs b/devices/src/legacy/uart_pl011.rs index 6a4af7161..f87b00850 100644 --- a/devices/src/legacy/uart_pl011.rs +++ b/devices/src/legacy/uart_pl011.rs @@ -339,7 +339,7 @@ impl BusDevice for Pl011 { fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option> { if data.len() <= 4 { - let v = read_le_u32(&data[..]); + let v = read_le_u32(&data); if let Err(e) = self.handle_write(offset, v) { warn!("Failed to write to PL011 device: {}", e); } @@ -496,11 +496,11 @@ mod tests { assert_eq!(intr_evt.read().unwrap(), 2); let mut data = [0u8]; - pl011.read(0, UARTDR as u64, &mut data[..]); + pl011.read(0, UARTDR as u64, &mut data); assert_eq!(data[0], b'a'); - pl011.read(0, UARTDR as u64, &mut data[..]); + pl011.read(0, UARTDR as u64, &mut data); assert_eq!(data[0], b'b'); - pl011.read(0, UARTDR as u64, &mut data[..]); + pl011.read(0, UARTDR as u64, &mut data); assert_eq!(data[0], b'c'); } }