diff --git a/arch/src/x86_64/cpu_profile/mod.rs b/arch/src/x86_64/cpu_profile/mod.rs
index 7c725d52e..61f969ba1 100644
--- a/arch/src/x86_64/cpu_profile/mod.rs
+++ b/arch/src/x86_64/cpu_profile/mod.rs
@@ -17,6 +17,7 @@ const TILECFG_MASK: u32 = 1_u32 << AMX_TILECFG_BIT;
 const TILEDATA_MASK: u32 = 1_u32 << AMX_TILEDATA_BIT;
 
 pub mod cpuid_adjustments;
+pub mod msr_adjustments;
 
 // TODO: Auto generate the CpuProfile enum with a build script once we introduce user facing CPU profiles.
 
diff --git a/arch/src/x86_64/cpu_profile/msr_adjustments.rs b/arch/src/x86_64/cpu_profile/msr_adjustments.rs
new file mode 100644
index 000000000..ddf66b88b
--- /dev/null
+++ b/arch/src/x86_64/cpu_profile/msr_adjustments.rs
@@ -0,0 +1,18 @@
+// Copyright © 2026 Cyberus Technology GmbH
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+use serde::{Deserialize, Serialize};
+
+use crate::x86_64::helpers::{deserialize_u32_hex, serialize_u32_hex};
+
+/// The register address of an MSR
+#[derive(Debug, Copy, Clone, Eq, PartialEq, Serialize, Deserialize)]
+pub struct RegisterAddress(
+    #[serde(
+        serialize_with = "serialize_u32_hex",
+        deserialize_with = "deserialize_u32_hex"
+    )]
+    pub u32,
+);