hypervisor: Extend interrupt handling for legacy IRQ

On x86 MSHV guests only used to support MSI based interrupts via IOAPIC
but ARM64 guests uses legacy interrupt for its functioning. Thus, extend
the logic to create routing entry to support legacy interrupts for ARM64
guests on MSHV.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor/src/mshv/aarch64/gic/mod.rs

@@ -32,6 +32,8 @@ pub struct MshvGicV2M {
     pub vcpu_count: u64,
 }
 
+pub const BASE_SPI_IRQ: u32 = 32;
+
 #[derive(Clone, Default, Serialize, Deserialize)]
 pub struct MshvGicV2MState {}
 

hypervisor/src/mshv/mod.rs

@@ -44,7 +44,7 @@ use std::os::unix::io::AsRawFd;
 use std::sync::Mutex;
 
 #[cfg(target_arch = "aarch64")]
-use aarch64::gic::MshvGicV2M;
+use aarch64::gic::{MshvGicV2M, BASE_SPI_IRQ};
 #[cfg(target_arch = "aarch64")]
 pub use aarch64::VcpuMshvState;
 #[cfg(feature = "sev_snp")]
@@ -2073,9 +2073,20 @@ impl vm::Vm for MshvVm {
                 data: cfg.data,
             }
             .into(),
+            #[cfg(target_arch = "x86_64")]
             _ => {
                 unreachable!()
             }
+            #[cfg(target_arch = "aarch64")]
+            InterruptSourceConfig::LegacyIrq(cfg) => mshv_user_irq_entry {
+                gsi,
+                // In order to get IRQ line we need to add `BASE_SPI_IRQ` to the pin number
+                // as `BASE_SPI_IRQ` is the base SPI interrupt number exposed via FDT to the
+                // guest.
+                data: cfg.pin + BASE_SPI_IRQ,
+                ..Default::default()
+            }
+            .into(),
         }
     }