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hypervisor: Switch to use the new StandardRegisters

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With this we are removing the CloudHypervisor definition of
StandardRegisters instead using an enum which contains different
variants of StandardRegisters coming from their bindigs crate.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
This commit is contained in:
Jinank Jain
2024-08-02 16:03:22 +05:30
committed by Bo Chen
parent 8f3bd4d9ec
commit 4c99aea6c4
12 changed files with 184 additions and 246 deletions
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6
hypervisor/src/mshv/mod.rs
View File

@@ -434,14 +434,14 @@ impl cpu::Vcpu for MshvVcpu {
/// Returns StandardRegisters with default value set
///
#[cfg(target_arch = "x86_64")]
fn create_standard_regs(&self) -> crate::arch::x86::StandardRegisters {
fn create_standard_regs(&self) -> crate::StandardRegisters {
mshv_bindings::StandardRegisters::default().into()
}
#[cfg(target_arch = "x86_64")]
///
/// Returns the vCPU general purpose registers.
///
fn get_regs(&self) -> cpu::Result<crate::arch::x86::StandardRegisters> {
fn get_regs(&self) -> cpu::Result<crate::StandardRegisters> {
Ok(self
.fd
.get_regs()
@@ -453,7 +453,7 @@ impl cpu::Vcpu for MshvVcpu {
///
/// Sets the vCPU general purpose registers.
///
fn set_regs(&self, regs: &crate::arch::x86::StandardRegisters) -> cpu::Result<()> {
fn set_regs(&self, regs: &crate::StandardRegisters) -> cpu::Result<()> {
let regs = (*regs).into();
self.fd
.set_regs(&regs)

51
hypervisor/src/mshv/x86_64/mod.rs
View File

@@ -9,7 +9,6 @@
//
use crate::arch::x86::{
CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters,
StandardRegisters,
};
use serde::{Deserialize, Serialize};
use std::fmt;
@@ -73,56 +72,6 @@ impl fmt::Display for VcpuMshvState {
}
}
impl From<StandardRegisters> for MshvStandardRegisters {
fn from(regs: StandardRegisters) -> Self {
Self {
rax: regs.rax,
rbx: regs.rbx,
rcx: regs.rcx,
rdx: regs.rdx,
rsi: regs.rsi,
rdi: regs.rdi,
rsp: regs.rsp,
rbp: regs.rbp,
r8: regs.r8,
r9: regs.r9,
r10: regs.r10,
r11: regs.r11,
r12: regs.r12,
r13: regs.r13,
r14: regs.r14,
r15: regs.r15,
rip: regs.rip,
rflags: regs.rflags,
}
}
}
impl From<MshvStandardRegisters> for StandardRegisters {
fn from(regs: MshvStandardRegisters) -> Self {
Self {
rax: regs.rax,
rbx: regs.rbx,
rcx: regs.rcx,
rdx: regs.rdx,
rsi: regs.rsi,
rdi: regs.rdi,
rsp: regs.rsp,
rbp: regs.rbp,
r8: regs.r8,
r9: regs.r9,
r10: regs.r10,
r11: regs.r11,
r12: regs.r12,
r13: regs.r13,
r14: regs.r14,
r15: regs.r15,
rip: regs.rip,
rflags: regs.rflags,
}
}
}
impl From<SegmentRegister> for MshvSegmentRegister {
fn from(s: SegmentRegister) -> Self {
Self {