hypervisor: Add api to set sev control register

This register configures the SEV feature control
state on a virtual processor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>

hypervisor/src/mshv/mod.rs

@@ -1241,6 +1241,18 @@ impl cpu::Vcpu for MshvVcpu {
         ]
         .to_vec()
     }
+
+    ///
+    /// Sets the AMD specific vcpu's sev control register.
+    ///
+    #[cfg(feature = "sev_snp")]
+    fn set_sev_control_register(&self, vmsa_pfn: u64) -> cpu::Result<()> {
+        let sev_control_reg = snp::get_sev_control_register(vmsa_pfn);
+
+        self.fd
+            .set_sev_control_register(sev_control_reg)
+            .map_err(|e| cpu::HypervisorCpuError::SetSevControlRegister(e.into()))
+    }
 }
 
 impl MshvVcpu {