hypervisor: Add api to set sev control register

This register configures the SEV feature control
state on a virtual processor.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Signed-off-by: Muminul Islam <muislam@microsoft.com>

hypervisor/src/cpu.rs

@@ -272,6 +272,12 @@ pub enum HypervisorCpuError {
     ///
     #[error("Failed to get CPUID entries: {0}")]
     GetCpuidVales(#[source] anyhow::Error),
+    ///
+    /// Setting SEV control register error
+    ///
+    #[cfg(feature = "sev_snp")]
+    #[error("Failed to set sev control register: {0}")]
+    SetSevControlRegister(#[source] anyhow::Error),
 }
 
 #[derive(Debug)]
@@ -495,4 +501,8 @@ pub trait Vcpu: Send + Sync {
     ) -> Result<[u32; 4]> {
         unimplemented!()
     }
+    #[cfg(feature = "mshv")]
+    fn set_sev_control_register(&self, _reg: u64) -> Result<()> {
+        unimplemented!()
+    }
 }

hypervisor/src/mshv/mod.rs

@@ -1241,6 +1241,18 @@ impl cpu::Vcpu for MshvVcpu {
         ]
         .to_vec()
     }
+
+    ///
+    /// Sets the AMD specific vcpu's sev control register.
+    ///
+    #[cfg(feature = "sev_snp")]
+    fn set_sev_control_register(&self, vmsa_pfn: u64) -> cpu::Result<()> {
+        let sev_control_reg = snp::get_sev_control_register(vmsa_pfn);
+
+        self.fd
+            .set_sev_control_register(sev_control_reg)
+            .map_err(|e| cpu::HypervisorCpuError::SetSevControlRegister(e.into()))
+    }
 }
 
 impl MshvVcpu {