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hypervisor: provide a generic FpuState structure

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Signed-off-by: Wei Liu <liuwe@microsoft.com>
This commit is contained in:
Wei Liu
2022-07-15 12:35:10 +00:00
committed by Rob Bradford
parent 08135fa085
commit 6a8c0fc887
8 changed files with 105 additions and 19 deletions
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11
hypervisor/src/mshv/mod.rs
View File

@@ -37,7 +37,7 @@ use std::fs::File;
use std::os::unix::io::AsRawFd;
#[cfg(target_arch = "x86_64")]
use crate::arch::x86::{CpuIdEntry, SpecialRegisters, StandardRegisters};
use crate::arch::x86::{CpuIdEntry, FpuState, SpecialRegisters, StandardRegisters};
const DIRTY_BITMAP_CLEAR_DIRTY: u64 = 0x4;
const DIRTY_BITMAP_SET_DIRTY: u64 = 0x8;
@@ -317,17 +317,20 @@ impl cpu::Vcpu for MshvVcpu {
/// Returns the floating point state (FPU) from the vCPU.
///
fn get_fpu(&self) -> cpu::Result<FpuState> {
self.fd
Ok(self
.fd
.get_fpu()
.map_err(|e| cpu::HypervisorCpuError::GetFloatingPointRegs(e.into()))
.map_err(|e| cpu::HypervisorCpuError::GetFloatingPointRegs(e.into()))?
.into())
}
#[cfg(target_arch = "x86_64")]
///
/// Set the floating point state (FPU) of a vCPU.
///
fn set_fpu(&self, fpu: &FpuState) -> cpu::Result<()> {
let fpu: mshv_bindings::FloatingPointUnit = (*fpu).clone().into();
self.fd
.set_fpu(fpu)
.set_fpu(&fpu)
.map_err(|e| cpu::HypervisorCpuError::SetFloatingPointRegs(e.into()))
}

37
hypervisor/src/mshv/x86_64/mod.rs
View File

@@ -8,7 +8,7 @@
//
//
use crate::arch::x86::{
CpuIdEntry, DescriptorTable, SegmentRegister, SpecialRegisters, StandardRegisters,
CpuIdEntry, DescriptorTable, FpuState, SegmentRegister, SpecialRegisters, StandardRegisters,
};
use serde::{Deserialize, Serialize};
use std::fmt;
@@ -19,7 +19,7 @@ use std::fmt;
pub use {
mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion,
mshv_bindings::msr_entry as MsrEntry, mshv_bindings::CpuId, mshv_bindings::DebugRegisters,
mshv_bindings::FloatingPointUnit as FpuState, mshv_bindings::LapicState,
mshv_bindings::FloatingPointUnit, mshv_bindings::LapicState,
mshv_bindings::MiscRegs as MiscRegisters, mshv_bindings::MsrList,
mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs,
mshv_bindings::SegmentRegister as MshvSegmentRegister,
@@ -252,3 +252,36 @@ impl From<hv_cpuid_entry> for CpuIdEntry {
}
}
}
impl From<FloatingPointUnit> for FpuState {
fn from(s: FloatingPointUnit) -> Self {
Self {
fpr: s.fpr,
fcw: s.fcw,
fsw: s.fsw,
ftwx: s.ftwx,
last_opcode: s.last_opcode,
last_ip: s.last_ip,
last_dp: s.last_dp,
xmm: s.xmm,
mxcsr: s.mxcsr,
}
}
}
impl From<FpuState> for FloatingPointUnit {
fn from(s: FpuState) -> Self {
Self {
fpr: s.fpr,
fcw: s.fcw,
fsw: s.fsw,
ftwx: s.ftwx,
last_opcode: s.last_opcode,
last_ip: s.last_ip,
last_dp: s.last_dp,
xmm: s.xmm,
mxcsr: s.mxcsr,
..Default::default()
}
}
}