diff --git a/pci/src/msix.rs b/pci/src/msix.rs
index 49b379b02..05a1d8ce5 100644
--- a/pci/src/msix.rs
+++ b/pci/src/msix.rs
@@ -321,7 +321,13 @@ impl MsixConfig {
     }
 
     pub fn write_table(&mut self, offset: u64, data: &[u8]) {
-        assert!(data.len() == 4 || data.len() == 8);
+        if data.len() != 4 && data.len() != 8 {
+            error!(
+                "invalid MSI-X table write size: {} (allowed: 4 or 8)",
+                data.len()
+            );
+            return;
+        }
 
         let index: usize = (offset / MSIX_TABLE_ENTRIES_MODULO) as usize;
         let modulo_offset = offset % MSIX_TABLE_ENTRIES_MODULO;