devices: Extend the Bus trait to carry the device range base

With the range base for the IO/MMIO vm exit address, a device with
multiple ranges has all the needed information for resolving which of
its range the exit is coming from

Fixes: #87

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

devices/src/bus.rs

@@ -19,9 +19,9 @@ use std::sync::{Arc, Mutex};
 #[allow(unused_variables)]
 pub trait BusDevice: Send {
     /// Reads at `offset` from this device
-    fn read(&mut self, offset: u64, data: &mut [u8]) {}
+    fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {}
     /// Writes at `offset` into this device
-    fn write(&mut self, offset: u64, data: &[u8]) {}
+    fn write(&mut self, base: u64, offset: u64, data: &[u8]) {}
     /// Triggers the `irq_mask` interrupt on this device
     fn interrupt(&self, irq_mask: u32) {}
 }
@@ -137,11 +137,11 @@ impl Bus {
     ///
     /// Returns true on success, otherwise `data` is untouched.
     pub fn read(&self, addr: u64, data: &mut [u8]) -> bool {
-        if let Some((_base, offset, dev)) = self.resolve(addr) {
+        if let Some((base, offset, dev)) = self.resolve(addr) {
             // OK to unwrap as lock() failing is a serious error condition and should panic.
             dev.lock()
                 .expect("Failed to acquire device lock")
-                .read(offset, data);
+                .read(base, offset, data);
             true
         } else {
             false
@@ -152,11 +152,11 @@ impl Bus {
     ///
     /// Returns true on success, otherwise `data` is untouched.
     pub fn write(&self, addr: u64, data: &[u8]) -> bool {
-        if let Some((_base, offset, dev)) = self.resolve(addr) {
+        if let Some((base, offset, dev)) = self.resolve(addr) {
             // OK to unwrap as lock() failing is a serious error condition and should panic.
             dev.lock()
                 .expect("Failed to acquire device lock")
-                .write(offset, data);
+                .write(base, offset, data);
             true
         } else {
             false

devices/src/ioapic.rs

@@ -159,7 +159,7 @@ pub struct Ioapic {
 }
 
 impl BusDevice for Ioapic {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         assert!(data.len() == 4);
 
         debug!("IOAPIC_R @ offset 0x{:x}", offset);
@@ -176,7 +176,7 @@ impl BusDevice for Ioapic {
         LittleEndian::write_u32(data, value);
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         assert!(data.len() == 4);
 
         debug!("IOAPIC_W @ offset 0x{:x}", offset);

devices/src/legacy/i8042.rs

@@ -22,7 +22,7 @@ impl I8042Device {
 // registers: port 0x61 (I8042_PORT_B_REG, offset 0 from base of 0x61), and
 // port 0x64 (I8042_COMMAND_REG, offset 3 from base of 0x61).
 impl BusDevice for I8042Device {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         if data.len() == 1 && offset == 3 {
             data[0] = 0x0;
         } else if data.len() == 1 && offset == 0 {
@@ -32,7 +32,7 @@ impl BusDevice for I8042Device {
         }
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         if data.len() == 1 && data[0] == 0xfe && offset == 3 {
             if let Err(e) = self.reset_evt.write(1) {
                 println!("Error triggering i8042 reset event: {}", e);

devices/src/legacy/serial.rs

@@ -189,7 +189,7 @@ impl Serial {
 }
 
 impl BusDevice for Serial {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         if data.len() != 1 {
             return;
         }
@@ -219,7 +219,7 @@ impl BusDevice for Serial {
         };
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         if data.len() != 1 {
             return;
         }

pci/src/root.rs

@@ -198,7 +198,7 @@ impl PciConfigIo {
 }
 
 impl BusDevice for PciConfigIo {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         // `offset` is relative to 0xcf8
         let value = match offset {
             0...3 => self.config_address,
@@ -220,7 +220,7 @@ impl BusDevice for PciConfigIo {
         }
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         // `offset` is relative to 0xcf8
         match offset {
             o @ 0...3 => self.set_config_address(o, data),
@@ -255,7 +255,7 @@ impl PciConfigMmio {
 }
 
 impl BusDevice for PciConfigMmio {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         // Only allow reads to the register boundary.
         let start = offset as usize % 4;
         let end = start + data.len();
@@ -272,7 +272,7 @@ impl BusDevice for PciConfigMmio {
         }
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         if offset > u64::from(u32::max_value()) {
             return;
         }

vm-virtio/src/transport/pci_device.rs

@@ -607,11 +607,11 @@ impl PciDevice for VirtioPciDevice {
 }
 
 impl BusDevice for VirtioPciDevice {
-    fn read(&mut self, offset: u64, data: &mut [u8]) {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         self.read_bar(offset, data)
     }
 
-    fn write(&mut self, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
         self.write_bar(offset, data)
     }
 }