From 8248650e799457fee3068b0bf3b54ffcade4bce1 Mon Sep 17 00:00:00 2001 From: Damian Barabonkov Date: Thu, 2 Apr 2026 10:15:31 -0700 Subject: [PATCH] pci: Handle dword MSI-X control writes Some guests update the MSI-X capability through a 32-bit write at offset 0 instead of a 16-bit write at offset 2. Update the cached Message Control state for that path as well so MSI-X enablement stays in sync with the guest configuration. Add a short comment documenting why the dword write path also updates the cached MSI-X Message Control state. This is important for passthrough GPUs, where MSI-X interrupts are used during NVIDIA Fabric Manager registration. Without updating the cached state on the dword write path, interrupt delivery can remain stale and GPU initialization or fabric registration can fail. Signed-off-by: Damian Barabonkov --- pci/src/vfio.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/pci/src/vfio.rs b/pci/src/vfio.rs index 53c77a95c..0fa3ae836 100644 --- a/pci/src/vfio.rs +++ b/pci/src/vfio.rs @@ -158,6 +158,10 @@ impl VfioMsix { // Update "Message Control" word if offset == 2 && data.len() == 2 { self.bar.set_msg_ctl(LittleEndian::read_u16(data)); + } else if offset == 0 && data.len() == 4 { + // Some guests update MSI-X control through the dword config write path. + self.bar + .set_msg_ctl((LittleEndian::read_u32(data) >> 16) as u16); } let new_enabled = self.bar.enabled();