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pci: Address Rust 1.51.0 clippy issue (upper_case_acroynms)
warning: name `IORegion` contains a capitalized acronym
--> pci/src/configuration.rs:320:5
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320 | IORegion = 0x01,
| ^^^^^^^^ help: consider making the acronym lowercase, except the initial letter (notice the capitalization): `IoRegion`
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= help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#upper_case_acronyms
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
+62
-62
@@ -100,7 +100,7 @@ pub enum PciBridgeSubclass {
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PcmciaBridge = 0x05,
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NuBusBridge = 0x06,
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CardBusBridge = 0x07,
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RACEwayBridge = 0x08,
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RacEwayBridge = 0x08,
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PciToPciSemiTransparentBridge = 0x09,
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InfiniBrandToPciHostBridge = 0x0a,
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OtherBridgeDevice = 0x80,
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@@ -117,9 +117,9 @@ impl PciSubclass for PciBridgeSubclass {
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#[derive(Copy, Clone)]
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pub enum PciSerialBusSubClass {
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Firewire = 0x00,
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ACCESSbus = 0x01,
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SSA = 0x02,
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USB = 0x03,
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Accessbus = 0x01,
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Ssa = 0x02,
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Usb = 0x03,
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}
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impl PciSubclass for PciSerialBusSubClass {
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@@ -132,15 +132,15 @@ impl PciSubclass for PciSerialBusSubClass {
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciMassStorageSubclass {
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SCSIStorage = 0x00,
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IDEInterface = 0x01,
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ScsiStorage = 0x00,
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IdeInterface = 0x01,
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FloppyController = 0x02,
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IPIController = 0x03,
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RAIDController = 0x04,
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ATAController = 0x05,
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SATAController = 0x06,
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SerialSCSIController = 0x07,
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NVMController = 0x08,
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IpiController = 0x03,
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RaidController = 0x04,
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AtaController = 0x05,
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SataController = 0x06,
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SerialScsiController = 0x07,
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NvmController = 0x08,
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MassStorage = 0x80,
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}
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@@ -156,11 +156,11 @@ impl PciSubclass for PciMassStorageSubclass {
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pub enum PciNetworkControllerSubclass {
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EthernetController = 0x00,
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TokenRingController = 0x01,
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FDDIController = 0x02,
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ATMController = 0x03,
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ISDNController = 0x04,
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FddiController = 0x02,
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AtmController = 0x03,
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IsdnController = 0x04,
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WorldFipController = 0x05,
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PICMGController = 0x06,
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PicmgController = 0x06,
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InfinibandController = 0x07,
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FabricController = 0x08,
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NetworkController = 0x80,
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@@ -186,55 +186,55 @@ pub trait PciProgrammingInterface {
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#[allow(dead_code)]
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#[allow(non_camel_case_types)]
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#[repr(C)]
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pub enum PciCapabilityID {
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ListID = 0,
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pub enum PciCapabilityId {
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ListId = 0,
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PowerManagement = 0x01,
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AcceleratedGraphicsPort = 0x02,
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VitalProductData = 0x03,
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SlotIdentification = 0x04,
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MessageSignalledInterrupts = 0x05,
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CompactPCIHotSwap = 0x06,
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PCIX = 0x07,
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CompactPciHotSwap = 0x06,
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PciX = 0x07,
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HyperTransport = 0x08,
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VendorSpecific = 0x09,
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Debugport = 0x0A,
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CompactPCICentralResourceControl = 0x0B,
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PCIStandardHotPlugController = 0x0C,
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BridgeSubsystemVendorDeviceID = 0x0D,
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AGPTargetPCIPCIbridge = 0x0E,
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CompactPciCentralResourceControl = 0x0B,
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PciStandardHotPlugController = 0x0C,
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BridgeSubsystemVendorDeviceId = 0x0D,
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AgpTargetPciPcibridge = 0x0E,
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SecureDevice = 0x0F,
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PCIExpress = 0x10,
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MSIX = 0x11,
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SATADataIndexConf = 0x12,
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PCIAdvancedFeatures = 0x13,
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PCIEnhancedAllocation = 0x14,
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PciExpress = 0x10,
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MsiX = 0x11,
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SataDataIndexConf = 0x12,
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PciAdvancedFeatures = 0x13,
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PciEnhancedAllocation = 0x14,
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}
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impl From<u8> for PciCapabilityID {
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impl From<u8> for PciCapabilityId {
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fn from(c: u8) -> Self {
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match c {
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0 => PciCapabilityID::ListID,
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0x01 => PciCapabilityID::PowerManagement,
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0x02 => PciCapabilityID::AcceleratedGraphicsPort,
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0x03 => PciCapabilityID::VitalProductData,
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0x04 => PciCapabilityID::SlotIdentification,
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0x05 => PciCapabilityID::MessageSignalledInterrupts,
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0x06 => PciCapabilityID::CompactPCIHotSwap,
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0x07 => PciCapabilityID::PCIX,
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0x08 => PciCapabilityID::HyperTransport,
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0x09 => PciCapabilityID::VendorSpecific,
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0x0A => PciCapabilityID::Debugport,
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0x0B => PciCapabilityID::CompactPCICentralResourceControl,
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0x0C => PciCapabilityID::PCIStandardHotPlugController,
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0x0D => PciCapabilityID::BridgeSubsystemVendorDeviceID,
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0x0E => PciCapabilityID::AGPTargetPCIPCIbridge,
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0x0F => PciCapabilityID::SecureDevice,
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0x10 => PciCapabilityID::PCIExpress,
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0x11 => PciCapabilityID::MSIX,
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0x12 => PciCapabilityID::SATADataIndexConf,
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0x13 => PciCapabilityID::PCIAdvancedFeatures,
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0x14 => PciCapabilityID::PCIEnhancedAllocation,
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_ => PciCapabilityID::ListID,
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0 => PciCapabilityId::ListId,
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0x01 => PciCapabilityId::PowerManagement,
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0x02 => PciCapabilityId::AcceleratedGraphicsPort,
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0x03 => PciCapabilityId::VitalProductData,
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0x04 => PciCapabilityId::SlotIdentification,
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0x05 => PciCapabilityId::MessageSignalledInterrupts,
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0x06 => PciCapabilityId::CompactPciHotSwap,
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0x07 => PciCapabilityId::PciX,
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0x08 => PciCapabilityId::HyperTransport,
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0x09 => PciCapabilityId::VendorSpecific,
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0x0A => PciCapabilityId::Debugport,
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0x0B => PciCapabilityId::CompactPciCentralResourceControl,
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0x0C => PciCapabilityId::PciStandardHotPlugController,
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0x0D => PciCapabilityId::BridgeSubsystemVendorDeviceId,
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0x0E => PciCapabilityId::AgpTargetPciPcibridge,
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0x0F => PciCapabilityId::SecureDevice,
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0x10 => PciCapabilityId::PciExpress,
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0x11 => PciCapabilityId::MsiX,
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0x12 => PciCapabilityId::SataDataIndexConf,
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0x13 => PciCapabilityId::PciAdvancedFeatures,
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0x14 => PciCapabilityId::PciEnhancedAllocation,
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_ => PciCapabilityId::ListId,
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}
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}
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}
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@@ -242,7 +242,7 @@ impl From<u8> for PciCapabilityID {
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/// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
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pub trait PciCapability {
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fn bytes(&self) -> &[u8];
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fn id(&self) -> PciCapabilityID;
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fn id(&self) -> PciCapabilityId;
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}
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fn encode_32_bits_bar_size(bar_size: u32) -> Option<u32> {
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@@ -317,7 +317,7 @@ pub struct PciConfiguration {
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#[derive(Copy, Clone, PartialEq, Serialize, Deserialize)]
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pub enum PciBarRegionType {
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Memory32BitRegion = 0,
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IORegion = 0x01,
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IoRegion = 0x01,
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Memory64BitRegion = 0x04,
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}
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@@ -572,7 +572,7 @@ impl PciConfiguration {
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.checked_add(config.size - 1)
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.ok_or(Error::BarAddressInvalid(config.addr, config.size))?;
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match config.region_type {
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PciBarRegionType::Memory32BitRegion | PciBarRegionType::IORegion => {
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PciBarRegionType::Memory32BitRegion | PciBarRegionType::IoRegion => {
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if end_addr > u64::from(u32::max_value()) {
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return Err(Error::BarAddressInvalid(config.addr, config.size));
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}
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@@ -614,7 +614,7 @@ impl PciConfiguration {
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BAR_MEM_ADDR_MASK,
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config.prefetchable as u32 | config.region_type as u32,
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),
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PciBarRegionType::IORegion => (BAR_IO_ADDR_MASK, config.region_type as u32),
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PciBarRegionType::IoRegion => (BAR_IO_ADDR_MASK, config.region_type as u32),
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};
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self.registers[bar_idx] = ((config.addr as u32) & mask) | lower_bits;
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@@ -711,7 +711,7 @@ impl PciConfiguration {
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}
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self.last_capability = Some((cap_offset, total_len));
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if cap_data.id() == PciCapabilityID::MSIX {
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if cap_data.id() == PciCapabilityId::MsiX {
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self.msix_cap_reg_idx = Some(cap_offset / 4);
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}
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@@ -1005,8 +1005,8 @@ mod tests {
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self.as_slice()
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}
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fn id(&self) -> PciCapabilityID {
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PciCapabilityID::VendorSpecific
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fn id(&self) -> PciCapabilityId {
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PciCapabilityId::VendorSpecific
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}
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}
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@@ -1056,11 +1056,11 @@ mod tests {
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}
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#[derive(Copy, Clone)]
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enum TestPI {
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enum TestPi {
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Test = 0x5a,
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}
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impl PciProgrammingInterface for TestPI {
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impl PciProgrammingInterface for TestPi {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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@@ -1074,7 +1074,7 @@ mod tests {
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0x1,
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PciClassCode::MultimediaController,
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&PciMultimediaSubclass::AudioController,
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Some(&TestPI::Test),
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Some(&TestPi::Test),
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PciHeaderType::Device,
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0xABCD,
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0x2468,
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