kata-containers/cloud-hypervisor
1
0
Fork 0
mirror of https://github.com/cloud-hypervisor/cloud-hypervisor.git synced 2026-08-05 02:19:16 +00:00
Code Issues Packages Projects Releases Wiki Activity

vmm: Set a default maximum physical address size

Browse Source 
When using PVH for booting (which we use for all firmwares and direct
kernel boot) the Linux kernel does not configure LA57 correctly. As such
we need to limit the address space to the maximum 4-level paging address
space.

If the user knows that their guest image can take advantage of the
5-level addressing and they need it for their workload then they can
increase the physical address space appropriately.

This PR removes the TDX specific handling as the new address space limit
is below the one that that code specified.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
2021-10-01 10:54:27 +01:00
committed by Bo Chen
parent 495e444ca6
commit 83066cf58e
5 changed files with 27 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files
vmm/src/vm.rs
+6 -36
View File
@@ -469,24 +469,10 @@ impl VmmOps for VmOps {
}
}
pub fn physical_bits(max_phys_bits: Option<u8>, #[cfg(feature = "tdx")] tdx_enabled: bool) -> u8 {
#[cfg(not(feature = "tdx"))]
pub fn physical_bits(max_phys_bits: u8) -> u8 {
let host_phys_bits = get_host_cpu_phys_bits();
#[cfg(feature = "tdx")]
let mut host_phys_bits = get_host_cpu_phys_bits();
#[cfg(feature = "tdx")]
if tdx_enabled {
// When running TDX guest, the Guest Physical Address space is limited
// by a shared bit that is located on bit 47 for 4 level paging, and on
// bit 51 for 5 level paging (when GPAW bit is 1). In order to keep
// things simple, and since a 47 bits address space is 128TiB large, we
// ensure to limit the physical addressable space to 47 bits when
// runnning TDX.
host_phys_bits = std::cmp::min(host_phys_bits, 47)
}
cmp::min(host_phys_bits, max_phys_bits.unwrap_or(host_phys_bits))
cmp::min(host_phys_bits, max_phys_bits)
}
pub const HANDLED_SIGNALS: [i32; 3] = [SIGWINCH, SIGTERM, SIGINT];
@@ -756,11 +742,7 @@ impl Vm {
#[cfg(target_arch = "x86_64")]
vm.enable_split_irq().unwrap();
let phys_bits = physical_bits(
config.lock().unwrap().cpus.max_phys_bits,
#[cfg(feature = "tdx")]
tdx_enabled,
);
let phys_bits = physical_bits(config.lock().unwrap().cpus.max_phys_bits);
let memory_manager = MemoryManager::new(
vm.clone(),
&config.lock().unwrap().memory.clone(),
@@ -832,11 +814,7 @@ impl Vm {
let memory_manager = if let Some(memory_manager_snapshot) =
snapshot.snapshots.get(MEMORY_MANAGER_SNAPSHOT_ID)
{
let phys_bits = physical_bits(
config.lock().unwrap().cpus.max_phys_bits,
#[cfg(feature = "tdx")]
config.lock().unwrap().tdx.is_some(),
);
let phys_bits = physical_bits(config.lock().unwrap().cpus.max_phys_bits);
MemoryManager::new_from_snapshot(
memory_manager_snapshot,
vm.clone(),
@@ -879,11 +857,7 @@ impl Vm {
let vm = hypervisor.create_vm().unwrap();
#[cfg(target_arch = "x86_64")]
vm.enable_split_irq().unwrap();
let phys_bits = physical_bits(
config.lock().unwrap().cpus.max_phys_bits,
#[cfg(feature = "tdx")]
config.lock().unwrap().tdx.is_some(),
);
let phys_bits = physical_bits(config.lock().unwrap().cpus.max_phys_bits);
let memory_manager = MemoryManager::new(
vm.clone(),
@@ -2396,11 +2370,7 @@ impl Snapshottable for Vm {
let common_cpuid = {
#[cfg(feature = "tdx")]
let tdx_enabled = self.config.lock().unwrap().tdx.is_some();
let phys_bits = physical_bits(
self.config.lock().unwrap().cpus.max_phys_bits,
#[cfg(feature = "tdx")]
tdx_enabled,
);
let phys_bits = physical_bits(self.config.lock().unwrap().cpus.max_phys_bits);
arch::generate_common_cpuid(
self.hypervisor.clone(),
None,