From 89ff0627e6ba04b4913e22f3f9def143d5ba0564 Mon Sep 17 00:00:00 2001
From: Jinank Jain <jinankjain@microsoft.com>
Date: Tue, 19 Mar 2024 21:03:51 +0530
Subject: [PATCH] hypervisor: mshv: Reduce msrs visibility to x86_64

Model Specific Registers (MSRs) are usually available on x86
architecture. So, let's reduce the visibility of MSRs to just x86
architecture.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
---
 hypervisor/src/mshv/mod.rs | 51 ++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 19 deletions(-)

diff --git a/hypervisor/src/mshv/mod.rs b/hypervisor/src/mshv/mod.rs
index 847a02786..1984911b1 100644
--- a/hypervisor/src/mshv/mod.rs
+++ b/hypervisor/src/mshv/mod.rs
@@ -290,27 +290,39 @@ impl hypervisor::Hypervisor for MshvHypervisor {
         )
         .map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?;
 
-        let msr_list = self.get_msr_list()?;
-        let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
-        let mut msrs: Vec<MsrEntry> = vec![
-            MsrEntry {
-                ..Default::default()
-            };
-            num_msrs
-        ];
-        let indices = msr_list.as_slice();
-        for (pos, index) in indices.iter().enumerate() {
-            msrs[pos].index = *index;
-        }
         let vm_fd = Arc::new(fd);
 
-        Ok(Arc::new(MshvVm {
-            fd: vm_fd,
-            msrs,
-            dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
-            #[cfg(feature = "sev_snp")]
-            sev_snp_enabled: mshv_vm_type == VmType::Snp,
-        }))
+        #[cfg(target_arch = "x86_64")]
+        {
+            let msr_list = self.get_msr_list()?;
+            let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
+            let mut msrs: Vec<MsrEntry> = vec![
+                MsrEntry {
+                    ..Default::default()
+                };
+                num_msrs
+            ];
+            let indices = msr_list.as_slice();
+            for (pos, index) in indices.iter().enumerate() {
+                msrs[pos].index = *index;
+            }
+
+            Ok(Arc::new(MshvVm {
+                fd: vm_fd,
+                msrs,
+                dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
+                #[cfg(feature = "sev_snp")]
+                sev_snp_enabled: mshv_vm_type == VmType::Snp,
+            }))
+        }
+
+        #[cfg(target_arch = "aarch64")]
+        {
+            Ok(Arc::new(MshvVm {
+                fd: vm_fd,
+                dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
+            }))
+        }
     }
 
     /// Create a mshv vm object and return the object as Vm trait object
@@ -1538,6 +1550,7 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
 /// Wrapper over Mshv VM ioctls.
 pub struct MshvVm {
     fd: Arc<VmFd>,
+    #[cfg(target_arch = "x86_64")]
     msrs: Vec<MsrEntry>,
     dirty_log_slots: Arc<RwLock<HashMap<u64, MshvDirtyLogSlot>>>,
     #[cfg(feature = "sev_snp")]