pci: Handle pending BAR reprogramming for VFIO devices properly

The way how we handle PCI configuration space for vfio and vfio-user
devices are different from the rest of PCI devices. Besides accesses to
BAR registers (trapped to access the shadowing PCI config space we
maintained), accesses to other registers (including the COMMAND
register) are handled directly by the underline vfio or vfio-user
device.

This patch adds the proper handling of pending BAR reprogramming for
vfio and vfio-user devices.

Signed-off-by: Bo Chen <bchen@crusoe.ai>

pci/src/vfio.rs

@@ -1292,7 +1292,26 @@ impl VfioCommon {
         // to the device region to update the MSI Enable bit.
         self.vfio_wrapper.write_config((reg + offset) as u32, data);
 
-        (Vec::new(), None)
+        // Return pending BAR repgrogramming if MSE bit is set
+        let mut ret_param = self.configuration.pending_bar_reprogram();
+        if !ret_param.is_empty() {
+            if self.read_config_register(crate::configuration::COMMAND_REG)
+                & crate::configuration::COMMAND_REG_MEMORY_SPACE_MASK
+                == crate::configuration::COMMAND_REG_MEMORY_SPACE_MASK
+            {
+                info!("BAR reprogramming parameter is returned: {:x?}", ret_param);
+                self.configuration.clear_pending_bar_reprogram();
+            } else {
+                info!(
+                    "MSE bit is disabled. No BAR reprogramming parameter is returned: {:x?}",
+                    ret_param
+                );
+
+                ret_param = Vec::new();
+            }
+        }
+
+        (ret_param, None)
     }
 
     pub(crate) fn read_config_register(&mut self, reg_idx: usize) -> u32 {