arch: aarch64: extract cache topology collection into a helper

Both arch/src/aarch64/fdt.rs and vmm/src/cpu.rs declared the same
~14 cache info locals (size/line_size/sets for L1D/L1I/L2/L3, plus
shared flags for L2/L3), checked for /sys/devices/system/cpu/cpu0/cache,
and populated those locals via get_cache_size /
get_cache_coherency_line_size / get_cache_number_of_sets /
get_cache_shared. Two near-identical ~30-line blocks.

Add a CacheTopologyInfo struct in arch/src/aarch64/cache.rs whose
field names mirror the existing locals, plus a read_cache_topology()
helper that returns None when the sysfs hierarchy is missing and
only queries get_cache_shared for L2/L3 when their size is non-zero
(preserving current behavior).

Both call sites now obtain the info via read_cache_topology() and
destructure it back into locals of the same name, so all downstream
references are unchanged.

Assisted-by: Copilot-CLI:Claude-Opus-4.7
Signed-off-by: Anirudh Rayabharam <anrayabh@microsoft.com>

arch/src/aarch64/cache.rs

@@ -9,6 +9,8 @@
 use std::fs;
 use std::path::Path;
 
+use log::warn;
+
 #[derive(Copy, Clone)]
 pub enum CacheLevel {
     /// L1 data cache
@@ -123,3 +125,64 @@ pub fn get_cache_shared(cache_level: CacheLevel) -> bool {
 
     result
 }
+
+#[derive(Default, Copy, Clone, Debug)]
+pub struct CacheTopologyInfo {
+    pub l1_d_cache_size: u32,
+    pub l1_d_cache_line_size: u32,
+    pub l1_d_cache_sets: u32,
+
+    pub l1_i_cache_size: u32,
+    pub l1_i_cache_line_size: u32,
+    pub l1_i_cache_sets: u32,
+
+    pub l2_cache_size: u32,
+    pub l2_cache_line_size: u32,
+    pub l2_cache_sets: u32,
+
+    pub l3_cache_size: u32,
+    pub l3_cache_line_size: u32,
+    pub l3_cache_sets: u32,
+
+    pub l2_cache_shared: bool,
+    pub l3_cache_shared: bool,
+}
+
+/// Reads cache topology information from sysfs for cpu0.
+pub fn read_cache_topology() -> Option<CacheTopologyInfo> {
+    let cache_path = Path::new("/sys/devices/system/cpu/cpu0/cache");
+    if !cache_path.exists() {
+        warn!("Cache topology information is not available in sysfs.");
+        return None;
+    }
+
+    let mut info = CacheTopologyInfo {
+        l1_d_cache_size: get_cache_size(CacheLevel::L1D),
+        l1_d_cache_line_size: get_cache_coherency_line_size(CacheLevel::L1D),
+        l1_d_cache_sets: get_cache_number_of_sets(CacheLevel::L1D),
+
+        l1_i_cache_size: get_cache_size(CacheLevel::L1I),
+        l1_i_cache_line_size: get_cache_coherency_line_size(CacheLevel::L1I),
+        l1_i_cache_sets: get_cache_number_of_sets(CacheLevel::L1I),
+
+        l2_cache_size: get_cache_size(CacheLevel::L2),
+        l2_cache_line_size: get_cache_coherency_line_size(CacheLevel::L2),
+        l2_cache_sets: get_cache_number_of_sets(CacheLevel::L2),
+
+        l3_cache_size: get_cache_size(CacheLevel::L3),
+        l3_cache_line_size: get_cache_coherency_line_size(CacheLevel::L3),
+        l3_cache_sets: get_cache_number_of_sets(CacheLevel::L3),
+
+        l2_cache_shared: false,
+        l3_cache_shared: false,
+    };
+
+    if info.l2_cache_size != 0 {
+        info.l2_cache_shared = get_cache_shared(CacheLevel::L2);
+    }
+    if info.l3_cache_size != 0 {
+        info.l3_cache_shared = get_cache_shared(CacheLevel::L3);
+    }
+
+    Some(info)
+}