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Revert "vmm: Move MemoryManager from I/O ports to MMIO region"

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This reverts commit 03108fb88b.
This commit is contained in:
Rob Bradford
2020-01-24 10:36:39 +00:00
committed by Sebastien Boeuf
parent 57ed006992
commit a34893a402
2 changed files with 16 additions and 38 deletions
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vmm/src/device_manager.rs
+8 -7
View File
@@ -523,15 +523,16 @@ impl DeviceManager {
#[cfg(feature = "acpi")] #[cfg(feature = "acpi")]
let memory_manager_clone = memory_manager.clone(); let memory_manager_clone = memory_manager.clone();
let memory_manager_device_base = memory_manager.lock().unwrap().device_base(); address_manager
.allocator
.lock()
.unwrap()
.allocate_io_addresses(Some(GuestAddress(0x0a00)), 0x18, None)
.ok_or(DeviceManagerError::AllocateIOPort)?;
address_manager address_manager
.mmio_bus .io_bus
.insert( .insert(memory_manager, 0xa00, 0x18)
memory_manager,
memory_manager_device_base.0,
MemoryManager::DEVICE_SIZE,
)
.map_err(DeviceManagerError::BusError)?; .map_err(DeviceManagerError::BusError)?;
Ok(DeviceManager { Ok(DeviceManager {
vmm/src/memory_manager.rs
+8 -31
View File
@@ -48,7 +48,6 @@ pub struct MemoryManager {
allocator: Arc<Mutex<SystemAllocator>>, allocator: Arc<Mutex<SystemAllocator>>,
current_ram: u64, current_ram: u64,
next_hotplug_slot: usize, next_hotplug_slot: usize,
device_base: GuestAddress,
} }
#[derive(Debug)] #[derive(Debug)]
@@ -190,8 +189,6 @@ impl BusDevice for MemoryManager {
} }
impl MemoryManager { impl MemoryManager {
pub const DEVICE_SIZE: u64 = 0x18;
pub fn new( pub fn new(
allocator: Arc<Mutex<SystemAllocator>>, allocator: Arc<Mutex<SystemAllocator>>,
fd: Arc<VmFd>, fd: Arc<VmFd>,
@@ -238,13 +235,6 @@ impl MemoryManager {
let mut hotplug_slots = Vec::with_capacity(HOTPLUG_COUNT); let mut hotplug_slots = Vec::with_capacity(HOTPLUG_COUNT);
hotplug_slots.resize_with(HOTPLUG_COUNT, HotPlugState::default); hotplug_slots.resize_with(HOTPLUG_COUNT, HotPlugState::default);
// Allocate some MMIO space for the device to be acessible from
let device_base = allocator
.lock()
.unwrap()
.allocate_mmio_addresses(None, MemoryManager::DEVICE_SIZE, None)
.ok_or(Error::MemoryRangeAllocation)?;
let memory_manager = Arc::new(Mutex::new(MemoryManager { let memory_manager = Arc::new(Mutex::new(MemoryManager {
guest_memory: guest_memory.clone(), guest_memory: guest_memory.clone(),
next_kvm_memory_slot: 0, next_kvm_memory_slot: 0,
@@ -259,7 +249,6 @@ impl MemoryManager {
allocator: allocator.clone(), allocator: allocator.clone(),
current_ram: boot_ram, current_ram: boot_ram,
next_hotplug_slot: 0, next_hotplug_slot: 0,
device_base,
})); }));
guest_memory.load().with_regions(|_, region| { guest_memory.load().with_regions(|_, region| {
@@ -369,7 +358,7 @@ impl MemoryManager {
.allocate_mmio_addresses(Some(start_addr), size as GuestUsize, None) .allocate_mmio_addresses(Some(start_addr), size as GuestUsize, None)
.ok_or(Error::MemoryRangeAllocation)?; .ok_or(Error::MemoryRangeAllocation)?;
// Update the slot so that it can be queried via the MMIO region // Update the slot so that it can be queried via the I/O port
let mut slot = &mut self.hotplug_slots[self.next_hotplug_slot]; let mut slot = &mut self.hotplug_slots[self.next_hotplug_slot];
slot.active = true; slot.active = true;
slot.inserting = true; slot.inserting = true;
@@ -471,10 +460,6 @@ impl MemoryManager {
Ok(false) Ok(false)
} }
} }
pub fn device_base(&self) -> GuestAddress {
self.device_base
}
} }
#[cfg(feature = "acpi")] #[cfg(feature = "acpi")]
@@ -606,7 +591,7 @@ impl Aml for MemoryMethods {
&aml::While::new( &aml::While::new(
&aml::LessThan::new(&aml::Local(0), &self.slots), &aml::LessThan::new(&aml::Local(0), &self.slots),
vec![ vec![
// Write slot number (in first argument) to MMIO region via field // Write slot number (in first argument) to I/O port via field
&aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Local(0)), &aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Local(0)),
// Check if MINS bit is set (inserting) // Check if MINS bit is set (inserting)
&aml::If::new( &aml::If::new(
@@ -659,7 +644,7 @@ impl Aml for MemoryMethods {
vec![ vec![
// Take lock defined above // Take lock defined above
&aml::Acquire::new("MLCK".into(), 0xfff), &aml::Acquire::new("MLCK".into(), 0xfff),
// Write slot number (in first argument) to MMIO region via field // Write slot number (in first argument) to I/O port via field
&aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Arg(0)), &aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Arg(0)),
&aml::Store::new(&aml::Local(0), &aml::ZERO), &aml::Store::new(&aml::Local(0), &aml::ZERO),
// Check if MEN_ bit is set, if so make the local variable 0xf (see _STA for details of meaning) // Check if MEN_ bit is set, if so make the local variable 0xf (see _STA for details of meaning)
@@ -685,7 +670,7 @@ impl Aml for MemoryMethods {
vec![ vec![
// Take lock defined above // Take lock defined above
&aml::Acquire::new("MLCK".into(), 0xfff), &aml::Acquire::new("MLCK".into(), 0xfff),
// Write slot number (in first argument) to MMIO region via field // Write slot number (in first argument) to I/O port via field
&aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Arg(0)), &aml::Store::new(&aml::Path::new("\\_SB_.MHPC.MSEL"), &aml::Arg(0)),
&aml::Name::new( &aml::Name::new(
"MR64".into(), "MR64".into(),
@@ -748,20 +733,12 @@ impl Aml for MemoryManager {
// I/O port for memory controller // I/O port for memory controller
&aml::Name::new( &aml::Name::new(
"_CRS".into(), "_CRS".into(),
&aml::ResourceTemplate::new(vec![&aml::AddressSpace::new_memory( &aml::ResourceTemplate::new(vec![&aml::IO::new(
aml::AddressSpaceCachable::NotCacheable, 0x0a00, 0x0a00, 0x01, 0x18,
true,
self.device_base.0,
self.device_base.0 + MemoryManager::DEVICE_SIZE - 1,
)]), )]),
), ),
// OpRegion and Fields map MMIO data into individual field values // OpRegion and Fields map I/O port into individual field values
&aml::OpRegion::new( &aml::OpRegion::new("MHPR".into(), aml::OpRegionSpace::SystemIO, 0xa00, 0x18),
"MHPR".into(),
aml::OpRegionSpace::SystemMemory,
self.device_base.0 as usize,
MemoryManager::DEVICE_SIZE as usize,
),
&aml::Field::new( &aml::Field::new(
"MHPR".into(), "MHPR".into(),
aml::FieldAccessType::DWord, aml::FieldAccessType::DWord,