From aaa3a114dd282ae66becbb573395ccb06707c6bf Mon Sep 17 00:00:00 2001 From: Jinank Jain Date: Wed, 7 May 2025 10:41:32 +0000 Subject: [PATCH] arch: hypervisor: Define PPI constants for ARM arch timer Currently PPI interrupt ID are hardcoded as numbers, it would be ideal to define them as constants and could be reused in other parts of the hypervisor crate. Signed-off-by: Jinank Jain --- arch/src/aarch64/fdt.rs | 13 +++++++++++-- hypervisor/src/arch/aarch64/regs.rs | 5 +++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/src/aarch64/fdt.rs b/arch/src/aarch64/fdt.rs index 60748f937..dcc86f347 100644 --- a/arch/src/aarch64/fdt.rs +++ b/arch/src/aarch64/fdt.rs @@ -15,6 +15,10 @@ use std::{cmp, fs, result, str}; use byteorder::{BigEndian, ByteOrder}; use hypervisor::arch::aarch64::gic::Vgic; +use hypervisor::arch::aarch64::regs::{ + AARCH64_ARCH_TIMER_HYP_IRQ, AARCH64_ARCH_TIMER_PHYS_NONSECURE_IRQ, + AARCH64_ARCH_TIMER_PHYS_SECURE_IRQ, AARCH64_ARCH_TIMER_VIRT_IRQ, +}; use thiserror::Error; use vm_fdt::{FdtWriter, FdtWriterResult}; use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError, GuestMemoryRegion}; @@ -708,9 +712,14 @@ fn create_clock_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> { fn create_timer_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> { // See - // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/interrupt-controller/arch_timer.txt + // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/timer/arm%2Carch_timer.yaml // These are fixed interrupt numbers for the timer device. - let irqs = [13, 14, 11, 10]; + let irqs = [ + AARCH64_ARCH_TIMER_PHYS_SECURE_IRQ, + AARCH64_ARCH_TIMER_PHYS_NONSECURE_IRQ, + AARCH64_ARCH_TIMER_VIRT_IRQ, + AARCH64_ARCH_TIMER_HYP_IRQ, + ]; let compatible = "arm,armv8-timer"; let mut timer_reg_cells: Vec = Vec::new(); diff --git a/hypervisor/src/arch/aarch64/regs.rs b/hypervisor/src/arch/aarch64/regs.rs index e1a51a848..bee5563da 100644 --- a/hypervisor/src/arch/aarch64/regs.rs +++ b/hypervisor/src/arch/aarch64/regs.rs @@ -216,3 +216,8 @@ arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5); arm64_sys_reg!(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0); arm64_sys_reg!(TTBR1_EL1, 3, 0, 2, 0, 1); arm64_sys_reg!(TCR_EL1, 3, 0, 2, 0, 2); + +pub const AARCH64_ARCH_TIMER_PHYS_SECURE_IRQ: u32 = 13; +pub const AARCH64_ARCH_TIMER_PHYS_NONSECURE_IRQ: u32 = 14; +pub const AARCH64_ARCH_TIMER_VIRT_IRQ: u32 = 11; +pub const AARCH64_ARCH_TIMER_HYP_IRQ: u32 = 10;