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misc: clippy: add semicolon_if_nothing_returned

Browse Source 
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com
This commit is contained in:
Philipp Schuster
2025-11-18 12:26:21 +01:00
committed by Rob Bradford
parent ea4f07d3bf
commit b4c62bf159
64 changed files with 244 additions and 236 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
devices/src/acpi.rs
View File

@@ -44,7 +44,7 @@ impl AcpiShutdownDevice {
impl BusDevice for AcpiShutdownDevice {
// Spec has all fields as zero
fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
data.fill(0)
data.fill(0);
}
fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
@@ -213,7 +213,7 @@ impl Aml for AcpiGedDevice {
),
],
)
.to_aml_bytes(sink)
.to_aml_bytes(sink);
}
}

2
devices/src/ivshmem.rs
View File

@@ -209,7 +209,7 @@ impl IvshmemDevice {
impl BusDevice for IvshmemDevice {
fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.read_bar(base, offset, data)
self.read_bar(base, offset, data);
}
fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {

2
devices/src/legacy/cmos.rs
View File

@@ -87,7 +87,7 @@ impl BusDevice for Cmos {
}
}
} else {
self.data[(self.index & INDEX_MASK) as usize] = data[0]
self.data[(self.index & INDEX_MASK) as usize] = data[0];
}
}
o => warn!("bad write offset on CMOS device: {o}"),

2
devices/src/legacy/debug_port.rs
View File

@@ -62,7 +62,7 @@ impl DebugPort {
impl BusDevice for DebugPort {
fn read(&mut self, _base: u64, _offset: u64, _data: &mut [u8]) {
error!("Invalid read to debug port")
error!("Invalid read to debug port");
}
fn write(

6
devices/src/legacy/fw_cfg.rs
View File

@@ -442,7 +442,7 @@ impl FwCfg {
fw_cfg_item_list: Option<Vec<FwCfgItem>>,
) -> Result<()> {
if let Some(mem_size) = mem_size {
self.add_e820(mem_size)?
self.add_e820(mem_size)?;
}
if let Some(kernel) = kernel {
self.add_kernel_data(&kernel)?;
@@ -451,7 +451,7 @@ impl FwCfg {
self.add_kernel_cmdline(cmdline);
}
if let Some(initramfs) = initramfs {
self.add_initramfs_data(&initramfs)?
self.add_initramfs_data(&initramfs)?;
}
if let Some(fw_cfg_item_list) = fw_cfg_item_list {
for item in fw_cfg_item_list {
@@ -626,7 +626,7 @@ impl FwCfg {
&access_resp.0.to_be_bytes(),
GuestAddress(dma_address + core::mem::offset_of!(FwCfgDmaAccess, control_be) as u64),
) {
error!("fw_cfg: finishing dma: {e:?}")
error!("fw_cfg: finishing dma: {e:?}");
}
}

6
devices/src/legacy/fwdebug.rs
View File

@@ -26,9 +26,9 @@ impl BusDevice for FwDebugDevice {
/// Upon read return the magic value to indicate that there is a debug port
fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
if data.len() == 1 {
data[0] = 0xe9
data[0] = 0xe9;
} else {
error!("Invalid read size on debug port: {}", data.len())
error!("Invalid read size on debug port: {}", data.len());
}
}
@@ -36,7 +36,7 @@ impl BusDevice for FwDebugDevice {
if data.len() == 1 {
print!("{}", data[0] as char);
} else {
error!("Invalid write size on debug port: {}", data.len())
error!("Invalid write size on debug port: {}", data.len());
}
None

2
devices/src/legacy/gpio_pl061.rs
View File

@@ -261,7 +261,7 @@ impl BusDevice for Gpio {
let index = ((offset - GPIO_ID_LOW) >> 2) as usize;
value = u32::from(GPIO_ID[index]);
} else if offset < OFS_DATA {
value = self.data & ((offset >> 2) as u32)
value = self.data & ((offset >> 2) as u32);
} else {
value = match offset {
GPIODIR => self.dir,

8
devices/src/legacy/serial.rs
View File

@@ -215,7 +215,7 @@ impl Serial {
fn thr_empty(&mut self) -> Result<()> {
if self.is_thr_intr_enabled() {
self.add_intr_bit(IIR_THR_BIT);
self.trigger_interrupt()?
self.trigger_interrupt()?;
}
Ok(())
}
@@ -223,7 +223,7 @@ impl Serial {
fn recv_data(&mut self) -> Result<()> {
if self.is_recv_intr_enabled() {
self.add_intr_bit(IIR_RECV_BIT);
self.trigger_interrupt()?
self.trigger_interrupt()?;
}
self.line_status |= LSR_DATA_BIT;
Ok(())
@@ -240,10 +240,10 @@ impl Serial {
fn handle_write(&mut self, offset: u8, v: u8) -> Result<()> {
match offset {
DLAB_LOW if self.is_dlab_set() => {
self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(v)
self.baud_divisor = (self.baud_divisor & 0xff00) | u16::from(v);
}
DLAB_HIGH if self.is_dlab_set() => {
self.baud_divisor = (self.baud_divisor & 0x00ff) | ((u16::from(v)) << 8)
self.baud_divisor = (self.baud_divisor & 0x00ff) | ((u16::from(v)) << 8);
}
DATA => {
if self.is_loop() {

12
devices/src/pvmemcontrol.rs
View File

@@ -390,7 +390,7 @@ impl PvmemcontrolDevice {
.iter()
.skip(offset as usize)
.zip(data.iter_mut())
.for_each(|(src, dest)| *dest = *src)
.for_each(|(src, dest)| *dest = *src);
}
/// can only write to transport payload
@@ -402,7 +402,7 @@ impl PvmemcontrolDevice {
.iter_mut()
.skip(offset as usize)
.zip(data.iter())
.for_each(|(dest, src)| *dest = *src)
.for_each(|(dest, src)| *dest = *src);
}
fn find_connection(&self, conn: GuestConnection) -> Option<GuestAddress> {
@@ -650,13 +650,13 @@ impl PvmemcontrolBusDevice {
.ok_or(Error::InvalidConnection(conn.command))
})
.map(|gpa| self.handle_pvmemcontrol_request(gpa))
.unwrap_or_else(|err| warn!("{:?}", err));
.unwrap_or_else(|err| warn!("{err:?}"));
}
}
}
fn handle_guest_read(&self, offset: u64, data: &mut [u8]) {
self.dev.read().unwrap().read_transport(offset, data)
self.dev.read().unwrap().read_transport(offset, data);
}
}
@@ -760,7 +760,7 @@ impl PciDevice for PvmemcontrolPciDevice {
_mmio64_allocator: &mut AddressAllocator,
) -> Result<(), PciDeviceError> {
for bar in self.bar_regions.drain(..) {
mmio32_allocator.free(GuestAddress(bar.addr()), bar.size())
mmio32_allocator.free(GuestAddress(bar.addr()), bar.size());
}
Ok(())
}
@@ -805,7 +805,7 @@ impl Migratable for PvmemcontrolPciDevice {}
impl BusDeviceSync for PvmemcontrolBusDevice {
fn read(&self, _base: u64, offset: u64, data: &mut [u8]) {
self.handle_guest_read(offset, data)
self.handle_guest_read(offset, data);
}
fn write(&self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {

2
devices/src/pvpanic.rs
View File

@@ -141,7 +141,7 @@ impl PvPanicDevice {
impl BusDevice for PvPanicDevice {
fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.read_bar(base, offset, data)
self.read_bar(base, offset, data);
}
fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {