From b4dea599a3880503fe77b0dc869e294db78cb7a4 Mon Sep 17 00:00:00 2001 From: Anatol Belski Date: Sat, 16 May 2026 15:41:16 +0200 Subject: [PATCH] virtio-devices: Fix cap_len for VIRTIO_PCI_CAP_PCI_CFG VirtioPciCfgCap::new built its inner header via VirtioPciCap::new, which sized cap_len from the bare virtio_pci_cap layout, yielding 16. The emitted capability is VirtioPciCfgCap, which appends a four byte pci_cfg_data window, so the correct value is 20. The virtio 1.2 specification defines this cap as virtio_pci_cap followed by pci_cfg_data[4] and requires cap_len to cover the whole structure. Build the header inline so cap_len reflects the actual emitted size, matching VirtioPciNotifyCap and VirtioPciCap64. Signed-off-by: Anatol Belski --- virtio-devices/src/transport/pci_device.rs | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/virtio-devices/src/transport/pci_device.rs b/virtio-devices/src/transport/pci_device.rs index ac37c5893..c01955c38 100644 --- a/virtio-devices/src/transport/pci_device.rs +++ b/virtio-devices/src/transport/pci_device.rs @@ -9,6 +9,7 @@ use std::any::Any; use std::cmp; use std::io::Write; +use std::mem::size_of; use std::ops::Deref; use std::sync::atomic::{AtomicBool, AtomicU8, AtomicU16, AtomicUsize, Ordering}; use std::sync::{Arc, Barrier, Mutex}; @@ -208,7 +209,15 @@ impl PciCapability for VirtioPciCfgCap { impl VirtioPciCfgCap { fn new() -> Self { VirtioPciCfgCap { - cap: VirtioPciCap::new(PciCapabilityType::Pci, 0, 0, 0), + cap: VirtioPciCap { + cap_len: (size_of::() as u8) + VIRTIO_PCI_CAP_LEN_OFFSET, + cfg_type: PciCapabilityType::Pci as u8, + pci_bar: 0, + id: 0, + padding: [0; 2], + offset: Le32::from(0), + length: Le32::from(0), + }, ..Default::default() } }