From bbda07c388e434fba3484f83491ff82ebf1764b6 Mon Sep 17 00:00:00 2001
From: Rob Bradford <robert.bradford@intel.com>
Date: Thu, 17 Feb 2022 10:07:49 +0000
Subject: [PATCH] pci: Support DWORD/4-byte writes to the MSI-X control
 register

The PCI spec does not specify that the access has to be of a specific
size.

Fixes: #3714

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
(cherry picked from commit 9c6e7c4a4b8abf360bcc9d6c69405e9ed2842ee3)
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
---
 pci/src/configuration.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/pci/src/configuration.rs b/pci/src/configuration.rs
index 300d4c410..d3ff25096 100644
--- a/pci/src/configuration.rs
+++ b/pci/src/configuration.rs
@@ -740,6 +740,11 @@ impl PciConfiguration {
                         .lock()
                         .unwrap()
                         .set_msg_ctl(LittleEndian::read_u16(data));
+                } else if msix_cap_reg_idx == reg_idx && offset == 0 && data.len() == 4 {
+                    msix_config
+                        .lock()
+                        .unwrap()
+                        .set_msg_ctl((LittleEndian::read_u32(data) >> 16) as u16);
                 }
             }
         }