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pci: Keep detect_bar_reprogramming internal to PciConfiguration

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A BAR reprogramming of a PCI device will only happen when the (guest)
kernel write to its PCI config space, e.g. the detection of bar
reprogramming (`detect_bar_repgraomming()`) can be embedded to the PCI
config space write (`write_config_register()`). It simplifies APIs
exposed by the `struct PciConfiguration` and `trait PciDevice`. It also
prepares for easier handling of pending bar reprogramming when the MSE
bit of the COMMAND register is not enabled at the time of changing BAR
registers.

See: https://github.com/cloud-hypervisor/cloud-hypervisor/issues/7027#issuecomment-2853642959

Signed-off-by: Bo Chen <bchen@crusoe.ai>
This commit is contained in:
Bo Chen
2025-05-09 20:10:05 +00:00
parent 5814193722
commit cb52cf91df
8 changed files with 61 additions and 92 deletions
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13
pci/src/configuration.rs
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@@ -907,9 +907,14 @@ impl PciConfiguration {
(next + 3) & !3
}
pub fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
pub fn write_config_register(
&mut self,
reg_idx: usize,
offset: u64,
data: &[u8],
) -> Option<BarReprogrammingParams> {
if offset as usize + data.len() > 4 {
return;
return None;
}
// Handle potential write to MSI-X message control register
@@ -938,13 +943,15 @@ impl PciConfiguration {
4 => self.write_reg(reg_idx, LittleEndian::read_u32(data)),
_ => (),
}
self.detect_bar_reprogramming(reg_idx, data)
}
pub fn read_config_register(&self, reg_idx: usize) -> u32 {
self.read_reg(reg_idx)
}
pub fn detect_bar_reprogramming(
fn detect_bar_reprogramming(
&mut self,
reg_idx: usize,
data: &[u8],