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pci: Keep detect_bar_reprogramming internal to PciConfiguration

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A BAR reprogramming of a PCI device will only happen when the (guest)
kernel write to its PCI config space, e.g. the detection of bar
reprogramming (`detect_bar_repgraomming()`) can be embedded to the PCI
config space write (`write_config_register()`). It simplifies APIs
exposed by the `struct PciConfiguration` and `trait PciDevice`. It also
prepares for easier handling of pending bar reprogramming when the MSE
bit of the COMMAND register is not enabled at the time of changing BAR
registers.

See: https://github.com/cloud-hypervisor/cloud-hypervisor/issues/7027#issuecomment-2853642959

Signed-off-by: Bo Chen <bchen@crusoe.ai>
This commit is contained in:
Bo Chen
2025-05-09 20:10:05 +00:00
parent 5814193722
commit cb52cf91df
8 changed files with 61 additions and 92 deletions
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24
pci/src/vfio.rs
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@@ -1242,7 +1242,7 @@ impl VfioCommon {
reg_idx: usize,
offset: u64,
data: &[u8],
) -> Option<Arc<Barrier>> {
) -> (Option<BarReprogrammingParams>, Option<Arc<Barrier>>) {
// When the guest wants to write to a BAR, we trap it into
// our local configuration space. We're not reprogramming
// VFIO device.
@@ -1252,9 +1252,11 @@ impl VfioCommon {
// We keep our local cache updated with the BARs.
// We'll read it back from there when the guest is asking
// for BARs (see read_config_register()).
self.configuration
.write_config_register(reg_idx, offset, data);
return None;
return (
self.configuration
.write_config_register(reg_idx, offset, data),
None,
);
}
let reg = (reg_idx * PCI_CONFIG_REGISTER_SIZE) as u64;
@@ -1290,7 +1292,7 @@ impl VfioCommon {
// to the device region to update the MSI Enable bit.
self.vfio_wrapper.write_config((reg + offset) as u32, data);
None
(None, None)
}
pub(crate) fn read_config_register(&mut self, reg_idx: usize) -> u32 {
@@ -1850,7 +1852,7 @@ impl PciDevice for VfioPciDevice {
reg_idx: usize,
offset: u64,
data: &[u8],
) -> Option<Arc<Barrier>> {
) -> (Option<BarReprogrammingParams>, Option<Arc<Barrier>>) {
self.common.write_config_register(reg_idx, offset, data)
}
@@ -1858,16 +1860,6 @@ impl PciDevice for VfioPciDevice {
self.common.read_config_register(reg_idx)
}
fn detect_bar_reprogramming(
&mut self,
reg_idx: usize,
data: &[u8],
) -> Option<BarReprogrammingParams> {
self.common
.configuration
.detect_bar_reprogramming(reg_idx, data)
}
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.common.read_bar(base, offset, data)
}