From e214bb9eedede03f085ceb3cb9d0038ec3d44424 Mon Sep 17 00:00:00 2001 From: Muminul Islam Date: Thu, 17 Jun 2021 15:57:20 -0700 Subject: [PATCH] hypervisor: implement Display for MSHV VcpuState This functionality is useful for Snapshot/Restore debugging. Signed-off-by: Muminul Islam --- hypervisor/src/mshv/x86_64/mod.rs | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/hypervisor/src/mshv/x86_64/mod.rs b/hypervisor/src/mshv/x86_64/mod.rs index 11aae6248..7dfa6f309 100644 --- a/hypervisor/src/mshv/x86_64/mod.rs +++ b/hypervisor/src/mshv/x86_64/mod.rs @@ -7,9 +7,10 @@ // Copyright 2018-2019 CrowdStrike, Inc. // // - use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; use serde_derive::{Deserialize, Serialize}; +use std::fmt; + /// /// Export generically-named wrappers of mshv_bindings for Unix-based platforms /// @@ -36,6 +37,30 @@ pub struct VcpuMshvState { pub xsave: Xsave, } +impl fmt::Display for VcpuMshvState { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + let expected_num_msrs = self.msrs.as_fam_struct_ref().nmsrs as usize; + let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; + + for (i, entry) in self.msrs.as_slice().iter().enumerate() { + msr_entries[i][1] = entry.data; + msr_entries[i][0] = entry.index as u64; + } + write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- Local APIC: {:?} --- DBG: {:?} --- Xsave: {:?}", + msr_entries.len(), + msr_entries, + self.vcpu_events, + self.regs, + self.sregs, + self.fpu, + self.xcrs, + self.lapic, + self.dbg, + self.xsave, + ) + } +} + pub struct CreateDevice {} pub struct DeviceAttr {} pub struct IrqRouting {}