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pci: Add minimal PCI host emulation crate
This crate is based on the crosvm devices/src/pci implementation from 107edb3e We introduced a few changes: - This one is a standalone crate. The device crate does not carry any PCI specific bits. - Simplified PCI root configuration. We only carry a pointer to a PciConfiguration, not a wrapper around it. - Simplified BAR allocation API. All BARs from the PciDevice instance must be generated at once through the PciDevice.allocate_bars() method. - The PCI BARs are added to the MMIO bus from the PciRoot add_device() method. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Samuel Ortiz
298
pci/src/root.rs
Executable file
298
pci/src/root.rs
Executable file
@@ -0,0 +1,298 @@
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// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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use crate::configuration::{PciBridgeSubclass, PciClassCode, PciConfiguration, PciHeaderType};
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use crate::device::Error as PciDeviceError;
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use byteorder::{ByteOrder, LittleEndian};
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use devices::BusDevice;
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use std;
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use std::sync::Arc;
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use std::sync::Mutex;
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use vm_memory::{Address, GuestAddress, GuestUsize};
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const VENDOR_ID_INTEL: u16 = 0x8086;
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const DEVICE_ID_INTEL_VIRT_PCIE_HOST: u16 = 0x0d57;
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/// Errors for device manager.
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#[derive(Debug)]
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pub enum PciRootError {
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/// Could not allocate device address space for the device.
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AllocateDeviceAddrs(PciDeviceError),
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/// Could not allocate an IRQ number.
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AllocateIrq,
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/// Could not add a device to the mmio bus.
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MmioInsert(devices::BusError),
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}
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pub type Result<T> = std::result::Result<T, PciRootError>;
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/// Emulates the PCI Root bridge.
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pub struct PciRoot {
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/// Bus configuration for the root device.
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configuration: PciConfiguration,
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/// Devices attached to this bridge.
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devices: Vec<Arc<Mutex<dyn BusDevice>>>,
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}
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impl PciRoot {
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/// Create an empty PCI root bus.
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pub fn new(configuration: Option<PciConfiguration>) -> Self {
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if let Some(config) = configuration {
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PciRoot {
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configuration: config,
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devices: Vec::new(),
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}
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} else {
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PciRoot {
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configuration: PciConfiguration::new(
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VENDOR_ID_INTEL,
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DEVICE_ID_INTEL_VIRT_PCIE_HOST,
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PciClassCode::BridgeDevice,
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&PciBridgeSubclass::HostBridge,
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None,
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PciHeaderType::Bridge,
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0,
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0,
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),
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devices: Vec::new(),
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}
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}
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}
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/// Add a `device` to this root PCI bus.
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pub fn add_device(
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&mut self,
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device: Arc<Mutex<dyn BusDevice>>,
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bus: &mut devices::Bus,
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bars: Vec<(GuestAddress, GuestUsize)>,
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) -> Result<()> {
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for (address, size) in bars {
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bus.insert(device.clone(), address.raw_value(), size)
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.map_err(PciRootError::MmioInsert)?;
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}
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self.devices.push(device);
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Ok(())
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}
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pub fn config_space_read(
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&self,
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bus: usize,
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device: usize,
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_function: usize,
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register: usize,
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) -> u32 {
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// Only support one bus.
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if bus != 0 {
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return 0xffff_ffff;
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}
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match device {
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0 => {
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// If bus and device are both zero, then read from the root config.
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self.configuration.read_config_register(register)
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}
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dev_num => self.devices.get(dev_num - 1).map_or(0xffff_ffff, |d| {
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d.lock().unwrap().read_config_register(register)
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}),
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}
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}
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pub fn config_space_write(
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&mut self,
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bus: usize,
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device: usize,
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_function: usize,
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register: usize,
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offset: u64,
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data: &[u8],
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) {
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if offset as usize + data.len() > 4 {
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return;
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}
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// Only support one bus.
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if bus != 0 {
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return;
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}
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match device {
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0 => {
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// If bus and device are both zero, then read from the root config.
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self.configuration
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.write_config_register(register, offset, data);
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}
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dev_num => {
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if let Some(d) = self.devices.get(dev_num - 1) {
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d.lock()
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.unwrap()
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.write_config_register(register, offset, data);
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}
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}
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}
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}
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}
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/// Emulates PCI configuration access mechanism #1 (I/O ports 0xcf8 and 0xcfc).
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pub struct PciConfigIo {
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/// PCI root bridge.
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pci_root: PciRoot,
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/// Current address to read/write from (0xcf8 register, litte endian).
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config_address: u32,
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}
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impl PciConfigIo {
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pub fn new(pci_root: PciRoot) -> Self {
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PciConfigIo {
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pci_root,
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config_address: 0,
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}
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}
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fn config_space_read(&self) -> u32 {
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let enabled = (self.config_address & 0x8000_0000) != 0;
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if !enabled {
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return 0xffff_ffff;
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}
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let (bus, device, function, register) =
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parse_config_address(self.config_address & !0x8000_0000);
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self.pci_root
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.config_space_read(bus, device, function, register)
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}
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fn config_space_write(&mut self, offset: u64, data: &[u8]) {
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let enabled = (self.config_address & 0x8000_0000) != 0;
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if !enabled {
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return;
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}
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let (bus, device, function, register) =
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parse_config_address(self.config_address & !0x8000_0000);
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self.pci_root
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.config_space_write(bus, device, function, register, offset, data)
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}
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fn set_config_address(&mut self, offset: u64, data: &[u8]) {
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if offset as usize + data.len() > 4 {
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return;
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}
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let (mask, value): (u32, u32) = match data.len() {
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1 => (
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0x0000_00ff << (offset * 8),
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u32::from(data[0]) << (offset * 8),
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),
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2 => (
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0x0000_ffff << (offset * 16),
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(u32::from(data[1]) << 8 | u32::from(data[0])) << (offset * 16),
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),
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4 => (0xffff_ffff, LittleEndian::read_u32(data)),
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_ => return,
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};
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self.config_address = (self.config_address & !mask) | value;
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}
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}
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impl BusDevice for PciConfigIo {
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fn read(&mut self, offset: u64, data: &mut [u8]) {
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// `offset` is relative to 0xcf8
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let value = match offset {
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0...3 => self.config_address,
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4...7 => self.config_space_read(),
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_ => 0xffff_ffff,
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};
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// Only allow reads to the register boundary.
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let start = offset as usize % 4;
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let end = start + data.len();
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if end <= 4 {
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for i in start..end {
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data[i - start] = (value >> (i * 8)) as u8;
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}
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} else {
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for d in data {
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*d = 0xff;
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}
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}
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}
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fn write(&mut self, offset: u64, data: &[u8]) {
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// `offset` is relative to 0xcf8
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match offset {
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o @ 0...3 => self.set_config_address(o, data),
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o @ 4...7 => self.config_space_write(o - 4, data),
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_ => (),
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};
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}
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}
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/// Emulates PCI memory-mapped configuration access mechanism.
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pub struct PciConfigMmio {
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/// PCI root bridge.
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pci_root: PciRoot,
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}
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impl PciConfigMmio {
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pub fn new(pci_root: PciRoot) -> Self {
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PciConfigMmio { pci_root }
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}
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fn config_space_read(&self, config_address: u32) -> u32 {
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let (bus, device, function, register) = parse_config_address(config_address);
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self.pci_root
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.config_space_read(bus, device, function, register)
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}
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fn config_space_write(&mut self, config_address: u32, offset: u64, data: &[u8]) {
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let (bus, device, function, register) = parse_config_address(config_address);
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self.pci_root
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.config_space_write(bus, device, function, register, offset, data)
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}
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}
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impl BusDevice for PciConfigMmio {
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fn read(&mut self, offset: u64, data: &mut [u8]) {
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// Only allow reads to the register boundary.
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let start = offset as usize % 4;
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let end = start + data.len();
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if end > 4 || offset > u64::from(u32::max_value()) {
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for d in data {
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*d = 0xff;
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}
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return;
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}
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let value = self.config_space_read(offset as u32);
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for i in start..end {
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data[i - start] = (value >> (i * 8)) as u8;
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}
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}
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fn write(&mut self, offset: u64, data: &[u8]) {
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if offset > u64::from(u32::max_value()) {
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return;
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}
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self.config_space_write(offset as u32, offset % 4, data)
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}
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}
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// Parse the CONFIG_ADDRESS register to a (bus, device, function, register) tuple.
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fn parse_config_address(config_address: u32) -> (usize, usize, usize, usize) {
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const BUS_NUMBER_OFFSET: usize = 16;
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const BUS_NUMBER_MASK: u32 = 0x00ff;
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const DEVICE_NUMBER_OFFSET: usize = 11;
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const DEVICE_NUMBER_MASK: u32 = 0x1f;
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const FUNCTION_NUMBER_OFFSET: usize = 8;
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const FUNCTION_NUMBER_MASK: u32 = 0x07;
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const REGISTER_NUMBER_OFFSET: usize = 2;
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const REGISTER_NUMBER_MASK: u32 = 0x3f;
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let bus_number = ((config_address >> BUS_NUMBER_OFFSET) & BUS_NUMBER_MASK) as usize;
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let device_number = ((config_address >> DEVICE_NUMBER_OFFSET) & DEVICE_NUMBER_MASK) as usize;
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let function_number =
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((config_address >> FUNCTION_NUMBER_OFFSET) & FUNCTION_NUMBER_MASK) as usize;
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let register_number =
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((config_address >> REGISTER_NUMBER_OFFSET) & REGISTER_NUMBER_MASK) as usize;
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(bus_number, device_number, function_number, register_number)
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}
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