hypervisor: Implement support for fetching sys regs on MSHV

ARM64 system register constants are not 1:1 mapped to MSHV definition of
those registers so we need a small helper function to translate that
mapping before retrieving those system registers.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>

hypervisor/src/cpu.rs

@@ -323,7 +323,13 @@ pub enum HypervisorCpuError {
     #[cfg(feature = "sev_snp")]
     #[error("Failed to set sev control register: {0}")]
     SetSevControlRegister(#[source] anyhow::Error),
-
+    ///
+    /// Unsupported SysReg registers
+    ///
+    #[cfg(target_arch = "aarch64")]
+    #[error("Unsupported SysReg registers: {0}")]
+    UnsupportedSysReg(u32),
+    ///
     /// Error injecting NMI
     ///
     #[error("Failed to inject NMI")]

hypervisor/src/mshv/mod.rs

@@ -1328,8 +1328,20 @@ impl cpu::Vcpu for MshvVcpu {
     }
 
     #[cfg(target_arch = "aarch64")]
-    fn get_sys_reg(&self, _sys_reg: u32) -> cpu::Result<u64> {
+    fn get_sys_reg(&self, sys_reg: u32) -> cpu::Result<u64> {
-        unimplemented!()
+        let mshv_reg = self.sys_reg_to_mshv_reg(sys_reg)?;
+
+        let mut reg_assocs = [hv_register_assoc {
+            name: mshv_reg,
+            ..Default::default()
+        }];
+        self.fd
+            .get_reg(&mut reg_assocs)
+            .map_err(|e| cpu::HypervisorCpuError::GetRegister(e.into()))?;
+
+        // SAFETY: Accessing a union element from bindgen generated definition.
+        let res = unsafe { reg_assocs[0].value.reg64 };
+        Ok(res)
     }
 
     #[cfg(target_arch = "aarch64")]
@@ -1744,6 +1756,14 @@ impl MshvVcpu {
         }
         Ok(())
     }
+
+    #[cfg(target_arch = "aarch64")]
+    fn sys_reg_to_mshv_reg(&self, sys_regs: u32) -> cpu::Result<u32> {
+        match sys_regs {
+            regs::MPIDR_EL1 => Ok(hv_register_name_HV_ARM64_REGISTER_MPIDR_EL1),
+            _ => Err(cpu::HypervisorCpuError::UnsupportedSysReg(sys_regs)),
+        }
+    }
 }
 
 /// Wrapper over Mshv VM ioctls.