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vmm: hypervisor: Add a new interface to setup GICR for vcpus

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For MSHV arm64 guest, there is an in-hypervisor GICv2M emulation and for
that to work, it needs to be enlightened with the base address of GIC
redistributor exposed to guest via FDT.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
This commit is contained in:
Jinank Jain
2025-05-05 04:49:15 +00:00
parent eac44e6af0
commit fa2b5ca12b
4 changed files with 68 additions and 2 deletions
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8
hypervisor/src/cpu.rs
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@@ -590,7 +590,13 @@ pub trait Vcpu: Send + Sync {
fn set_sev_control_register(&self, _reg: u64) -> Result<()> {
unimplemented!()
}
///
/// Sets the value of GIC redistributor address
///
#[cfg(target_arch = "aarch64")]
fn set_gic_redistributor_addr(&self, _gicr_base_addr: u64) -> Result<()> {
Ok(())
}
#[cfg(target_arch = "x86_64")]
///
/// Trigger NMI interrupt