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misc: Remove unnecessary literal casts

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Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
2021-01-02 20:37:31 +00:00
committed by Sebastien Boeuf
parent 05cdef17f4
commit fabd63072b
8 changed files with 21 additions and 21 deletions
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4
hypervisor/src/arch/x86/emulator/instructions/mov.rs
View File

@@ -508,7 +508,7 @@ mod tests {
// Only run the first instruction.
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
assert_eq!(ip + 7 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
assert_eq!(ip + 7, vmm.cpu_state(cpu_id).unwrap().ip());
let new_rax: u64 = vmm
.cpu_state(cpu_id)
@@ -541,7 +541,7 @@ mod tests {
// Run the 2 first instructions.
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
assert_eq!(ip + 7 + 4 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
assert_eq!(ip + 7 + 4, vmm.cpu_state(cpu_id).unwrap().ip());
let rbx: u64 = vmm
.cpu_state(cpu_id)

6
hypervisor/src/mshv/mod.rs
View File

@@ -307,7 +307,7 @@ impl hypervisor::Hypervisor for MshvHypervisor {
/// Get the supported CpuID
///
fn get_cpuid(&self) -> hypervisor::Result<CpuId> {
Ok(CpuId::new(1 as usize))
Ok(CpuId::new(1))
}
#[cfg(target_arch = "x86_64")]
///
@@ -601,7 +601,7 @@ impl cpu::Vcpu for MshvVcpu {
}
hv_message_type_HVMSG_X64_MSR_INTERCEPT => {
let info = x.to_msr_info().unwrap();
if info.header.intercept_access_type == 0 as u8 {
if info.header.intercept_access_type == 0 {
debug!("msr read: {:x}", info.msr_number);
} else {
debug!("msr write: {:x}", info.msr_number);
@@ -935,7 +935,7 @@ impl vm::Vm for MshvVm {
let vcpu = MshvVcpu {
fd: vcpu_fd,
vp_index: id,
cpuid: CpuId::new(1 as usize),
cpuid: CpuId::new(1),
msrs: self.msrs.clone(),
ioeventfds: self.ioeventfds.clone(),
gsi_routes: self.gsi_routes.clone(),