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aarch64: Fix IRQ number setting for ACPI

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On FDT, VMM can allocate IRQ from 0 for devices.
But on ACPI, the lowest range below 32 has to be avoided.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
This commit is contained in:
Michael Zhao
2021-03-23 19:41:36 +08:00
committed by Sebastien Boeuf
parent efc583c13e
commit ff46fb69d0
9 changed files with 35 additions and 18 deletions
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20
arch/src/aarch64/fdt.rs
View File

@@ -16,7 +16,7 @@ use super::super::InitramfsConfig;
use super::get_fdt_addr;
use super::gic::GicDevice;
use super::layout::{
FDT_MAX_SIZE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, PCI_MMCONFIG_SIZE,
FDT_MAX_SIZE, IRQ_BASE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, PCI_MMCONFIG_SIZE,
PCI_MMCONFIG_START,
};
use vm_fdt::{FdtWriter, FdtWriterResult};
@@ -293,7 +293,11 @@ fn create_serial_node<T: DeviceInfoForFdt + Clone + Debug>(
) -> FdtWriterResult<()> {
let compatible = b"arm,pl011\0arm,primecell\0";
let serial_reg_prop = [dev_info.addr(), dev_info.length()];
let irq = [GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING];
let irq = [
GIC_FDT_IRQ_TYPE_SPI,
dev_info.irq() - IRQ_BASE,
IRQ_TYPE_EDGE_RISING,
];
let serial_node = fdt.begin_node(&format!("pl011@{:x}", dev_info.addr()))?;
fdt.property("compatible", compatible)?;
@@ -312,7 +316,11 @@ fn create_rtc_node<T: DeviceInfoForFdt + Clone + Debug>(
) -> FdtWriterResult<()> {
let compatible = b"arm,pl031\0arm,primecell\0";
let rtc_reg_prop = [dev_info.addr(), dev_info.length()];
let irq = [GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_LEVEL_HI];
let irq = [
GIC_FDT_IRQ_TYPE_SPI,
dev_info.irq() - IRQ_BASE,
IRQ_TYPE_LEVEL_HI,
];
let rtc_node = fdt.begin_node(&format!("rtc@{:x}", dev_info.addr()))?;
fdt.property("compatible", compatible)?;
@@ -332,7 +340,11 @@ fn create_gpio_node<T: DeviceInfoForFdt + Clone + Debug>(
// PL061 GPIO controller node
let compatible = b"arm,pl061\0arm,primecell\0";
let gpio_reg_prop = [dev_info.addr(), dev_info.length()];
let irq = [GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING];
let irq = [
GIC_FDT_IRQ_TYPE_SPI,
dev_info.irq() - IRQ_BASE,
IRQ_TYPE_EDGE_RISING,
];
let gpio_node = fdt.begin_node(&format!("pl061@{:x}", dev_info.addr()))?;
fdt.property("compatible", compatible)?;

2
arch/src/aarch64/gic/mod.rs
View File

@@ -149,7 +149,7 @@ pub mod kvm {
/* We need to tell the kernel how many irqs to support with this vgic.
* See the `layout` module for details.
*/
let nr_irqs: u32 = layout::IRQ_MAX - layout::IRQ_BASE + 1;
let nr_irqs: u32 = layout::IRQ_NUM;
let nr_irqs_ptr = &nr_irqs as *const u32;
Self::set_device_attribute(
gic_device.device(),

8
arch/src/aarch64/layout.rs
View File

@@ -97,8 +97,8 @@ pub const KERNEL_START: u64 = ACPI_START + ACPI_MAX_SIZE as u64;
// * less than 1023 and
// * a multiple of 32.
// We are setting up our interrupt controller to support a maximum of 256 interrupts.
/// First usable interrupt on aarch64.
pub const IRQ_BASE: u32 = 0;
/// First usable interrupt on aarch64
pub const IRQ_BASE: u32 = 32;
/// Last usable interrupt on aarch64.
pub const IRQ_MAX: u32 = 255;
/// Number of supported interrupts
pub const IRQ_NUM: u32 = 256;

2
arch/src/lib.rs
View File

@@ -76,7 +76,7 @@ pub mod aarch64;
pub use aarch64::{
arch_memory_regions, configure_system, configure_vcpu, fdt::DeviceInfoForFdt,
get_host_cpu_phys_bits, get_kernel_start, initramfs_load_addr, layout,
layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, layout::IRQ_MAX, EntryPoint,
layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, EntryPoint,
};
#[cfg(target_arch = "x86_64")]