misc: Use a more relaxed memory model when possible

When a total ordering between multiple atomic variables is not required
then use Ordering::Acquire with atomic loads and Ordering::Release with
atomic stores.

This will improve performance as this does not require a memory fence
on x86_64 which Ordering::SeqCst will use.

Add a comment to the code in the vCPU handling code where it operates on
multiple atomics to explain why Ordering::SeqCst is required.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

virtio-devices/src/balloon.rs

@@ -98,7 +98,7 @@ struct VirtioBalloonResizeReceiver {
 
 impl VirtioBalloonResizeReceiver {
     fn get_size(&self) -> u64 {
-        self.size.load(Ordering::SeqCst)
+        self.size.load(Ordering::Acquire)
     }
 
     fn send(&self, r: Result<(), Error>) -> Result<(), mpsc::SendError<Result<(), Error>>> {
@@ -134,7 +134,7 @@ impl VirtioBalloonResize {
     }
 
     pub fn work(&self, size: u64) -> Result<(), Error> {
-        self.size.store(size, Ordering::SeqCst);
+        self.size.store(size, Ordering::Release);
         self.evt.write(1).map_err(Error::EventFdWriteFail)?;
         self.rx.recv().map_err(Error::MpscRecvFail)?
     }