misc: Use a more relaxed memory model when possible

When a total ordering between multiple atomic variables is not required
then use Ordering::Acquire with atomic loads and Ordering::Release with
atomic stores.

This will improve performance as this does not require a memory fence
on x86_64 which Ordering::SeqCst will use.

Add a comment to the code in the vCPU handling code where it operates on
multiple atomics to explain why Ordering::SeqCst is required.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

virtio-devices/src/block.rs

@@ -108,7 +108,7 @@ impl<T: DiskFile> BlockEpollHandler<T> {
             let len;
             match Request::parse(&avail_desc, &mem) {
                 Ok(mut request) => {
-                    request.set_writeback(self.writeback.load(Ordering::SeqCst));
+                    request.set_writeback(self.writeback.load(Ordering::Acquire));
 
                     let mut disk_image_locked = self.disk_image.lock().unwrap();
                     let mut disk_image = disk_image_locked.deref_mut();
@@ -387,7 +387,7 @@ impl<T: DiskFile> Block<T> {
                 "writethrough"
             }
         );
-        self.writeback.store(writeback, Ordering::SeqCst);
+        self.writeback.store(writeback, Ordering::Release);
     }
 }