misc: Use a more relaxed memory model when possible

When a total ordering between multiple atomic variables is not required
then use Ordering::Acquire with atomic loads and Ordering::Release with
atomic stores.

This will improve performance as this does not require a memory fence
on x86_64 which Ordering::SeqCst will use.

Add a comment to the code in the vCPU handling code where it operates on
multiple atomics to explain why Ordering::SeqCst is required.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

virtio-devices/src/block_io_uring.rs

@@ -116,7 +116,7 @@ impl BlockIoUringEpollHandler {
 
         for avail_desc in queue.iter(&mem) {
             let mut request = Request::parse(&avail_desc, &mem).map_err(Error::RequestParsing)?;
-            request.set_writeback(self.writeback.load(Ordering::SeqCst));
+            request.set_writeback(self.writeback.load(Ordering::Acquire));
             if request
                 .execute_io_uring(
                     &mem,
@@ -428,7 +428,7 @@ impl BlockIoUring {
                 "writethrough"
             }
         );
-        self.writeback.store(writeback, Ordering::SeqCst);
+        self.writeback.store(writeback, Ordering::Release);
     }
 }