misc: Use a more relaxed memory model when possible

When a total ordering between multiple atomic variables is not required
then use Ordering::Acquire with atomic loads and Ordering::Release with
atomic stores.

This will improve performance as this does not require a memory fence
on x86_64 which Ordering::SeqCst will use.

Add a comment to the code in the vCPU handling code where it operates on
multiple atomics to explain why Ordering::SeqCst is required.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

vmm/src/cpu.rs

@@ -785,6 +785,11 @@ impl CpuManager {
                         // We enter a loop because park() could spuriously
                         // return. We will then park() again unless the
                         // pause boolean has been toggled.
+
+                        // Need to use Ordering::SeqCst as we have multiple
+                        // loads and stores to different atomics and we need
+                        // to see them in a consistent order in all threads
+
                         if vcpu_pause_signalled.load(Ordering::SeqCst) {
                             vcpu_run_interrupted.store(true, Ordering::SeqCst);
                             while vcpu_pause_signalled.load(Ordering::SeqCst) {