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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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0e7a1fc923
Using the existing layout module start documenting the major regions of RAM and those areas that are reserved. Some of the constants have also been renamed to be more consistent and some functions that returned constant variables have been replaced. Future commits will move more constants into this file to make it the canonical source of information about the memory layout. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
334 lines
12 KiB
Rust
334 lines
12 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use acpi_tables::{
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rsdp::RSDP,
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sdt::{GenericAddress, SDT},
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};
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use vm_memory::{GuestAddress, GuestMemoryMmap};
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use vm_memory::{Address, ByteValued, Bytes};
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use super::layout;
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#[repr(packed)]
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struct LocalAPIC {
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pub r#type: u8,
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pub length: u8,
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pub processor_id: u8,
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pub apic_id: u8,
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pub flags: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IOAPIC {
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pub r#type: u8,
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pub length: u8,
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pub ioapic_id: u8,
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_reserved: u8,
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pub apic_address: u32,
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pub gsi_base: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct InterruptSourceOverride {
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pub r#type: u8,
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pub length: u8,
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pub bus: u8,
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pub source: u8,
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pub gsi: u32,
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pub flags: u16,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct PCIRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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pub fn create_dsdt_table(
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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) -> SDT {
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/*
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The hex tables in this file are generated from the ASL below with:
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"iasl -tc <dsdt.asl>"
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As the output contains a table header that is not required the first 40 bytes
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should be disregarded.
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*/
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/*
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Device (_SB.PCI0)
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{
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Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
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Name (_ADR, Zero) // _ADR: Address
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Name (_SEG, Zero) // _SEG: PCI Segment
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Name (_UID, Zero) // _UID: Unique ID
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Name (SUPP, Zero)
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}
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Scope (_SB.PCI0)
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{
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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0x0000, // Range Minimum
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0x00FF, // Range Maximum
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0x0000, // Translation Offset
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0x0100, // Length
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,, )
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IO (Decode16,
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0x0CF8, // Range Minimum
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0x0CF8, // Range Maximum
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0x01, // Alignment
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0x08, // Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Granularity
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0x0000, // Range Minimum
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0x0CF7, // Range Maximum
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0x0000, // Translation Offset
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0x0CF8, // Length
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,, , TypeStatic, DenseTranslation)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Granularity
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0x0D00, // Range Minimum
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0xFFFF, // Range Maximum
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0x0000, // Translation Offset
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0xF300, // Length
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,, , TypeStatic, DenseTranslation)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x000A0000, // Range Minimum
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0x000BFFFF, // Range Maximum
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0x00000000, // Translation Offset
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0x00020000, // Length
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,, , AddressRangeMemory, TypeStatic)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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0xC0000000, // Range Minimum
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0xFEBFFFFF, // Range Maximum
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0x00000000, // Translation Offset
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0x3EC00000, // Length
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,, , AddressRangeMemory, TypeStatic)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x0000000000000000, // Granularity
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0x0000000800000000, // Range Minimum
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0x0000000FFFFFFFFF, // Range Maximum
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0x0000000000000000, // Translation Offset
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0x0000000800000000, // Length
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,, , AddressRangeMemory, TypeStatic)
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})
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}
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*/
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let mut pci_dsdt_data = [
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0x5Bu8, 0x82, 0x36, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x50, 0x43, 0x49, 0x30, 0x08, 0x5F, 0x48,
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0x49, 0x44, 0x0C, 0x41, 0xD0, 0x0A, 0x08, 0x08, 0x5F, 0x43, 0x49, 0x44, 0x0C, 0x41, 0xD0,
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0x0A, 0x03, 0x08, 0x5F, 0x41, 0x44, 0x52, 0x00, 0x08, 0x5F, 0x53, 0x45, 0x47, 0x00, 0x08,
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0x5F, 0x55, 0x49, 0x44, 0x00, 0x08, 0x53, 0x55, 0x50, 0x50, 0x00, 0x10, 0x41, 0x0B, 0x2E,
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0x5F, 0x53, 0x42, 0x5F, 0x50, 0x43, 0x49, 0x30, 0x08, 0x5F, 0x43, 0x52, 0x53, 0x11, 0x40,
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0x0A, 0x0A, 0x9C, 0x88, 0x0D, 0x00, 0x02, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x47, 0x01, 0xF8, 0x0C, 0xF8, 0x0C, 0x01, 0x08, 0x88, 0x0D, 0x00,
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0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF7, 0x0C, 0x00, 0x00, 0xF8, 0x0C, 0x88, 0x0D,
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0x00, 0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x0D, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xF3, 0x87,
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0x17, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0xFF, 0xFF,
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0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x87, 0x17, 0x00, 0x00, 0x0C,
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0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xBF, 0xFE, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xC0, 0x3E, 0x8A, 0x2B, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xFF, 0xFF,
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0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x79, 0x00,
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];
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// Patch the Range Minimum/Range Maximum/Length for the the 64-bit device area
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pci_dsdt_data[200..208].copy_from_slice(&(start_of_device_area.0).to_le_bytes());
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pci_dsdt_data[208..216].copy_from_slice(&end_of_device_area.0.to_le_bytes());
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pci_dsdt_data[224..232].copy_from_slice(
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&(end_of_device_area.unchecked_offset_from(start_of_device_area)).to_le_bytes(),
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);
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/*
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Device (_SB.COM1)
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{
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Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
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{
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0x00000004,
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}
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IO (Decode16,
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0x03F8, // Range Minimum
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0x03F8, // Range Maximum
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0x00, // Alignment
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0x08, // Length
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)
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})
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}
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*/
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let com1_dsdt_data = [
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0x5Bu8, 0x82, 0x36, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x43, 0x4F, 0x4D, 0x31, 0x08, 0x5F, 0x48,
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0x49, 0x44, 0x0C, 0x41, 0xD0, 0x05, 0x01, 0x08, 0x5F, 0x55, 0x49, 0x44, 0x00, 0x08, 0x5F,
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0x43, 0x52, 0x53, 0x11, 0x16, 0x0A, 0x13, 0x89, 0x06, 0x00, 0x03, 0x01, 0x04, 0x00, 0x00,
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0x00, 0x47, 0x01, 0xF8, 0x03, 0xF8, 0x03, 0x00, 0x08, 0x79, 0x00,
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];
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/*
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Name (\_S5, Package (0x01) // _S5_: S5 System State
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{
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0x05
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})
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*/
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let s5_sleep_data = [0x08u8, 0x5F, 0x53, 0x35, 0x5F, 0x12, 0x04, 0x01, 0x0A, 0x05];
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// DSDT
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let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append(pci_dsdt_data);
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if serial_enabled {
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dsdt.append(com1_dsdt_data);
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}
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dsdt.append(s5_sleep_data);
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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num_cpus: u8,
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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) -> GuestAddress {
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// RSDP is at the EBDA
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let rsdp_offset = layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(serial_enabled, start_of_device_area, end_of_device_area);
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let dsdt_offset = rsdp_offset.checked_add(RSDP::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = SDT::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// HW_REDUCED_ACPI and RESET_REG_SUP
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let fadt_flags: u32 = 1 << 20 | 1 << 10;
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facp.write(112, fadt_flags);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let mut madt = SDT::new(*b"APIC", 44, 5, *b"CLOUDH", *b"CHMADT ", 1);
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madt.write(36, super::mptable::APIC_DEFAULT_PHYS_BASE);
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for cpu in 0..num_cpus {
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let lapic = LocalAPIC {
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r#type: 0,
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length: 8,
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processor_id: cpu,
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apic_id: cpu,
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flags: 1,
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};
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madt.append(lapic);
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}
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madt.append(IOAPIC {
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r#type: 1,
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length: 12,
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ioapic_id: 0,
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apic_address: super::mptable::IO_APIC_DEFAULT_PHYS_BASE,
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gsi_base: 0,
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..Default::default()
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});
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madt.append(InterruptSourceOverride {
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r#type: 2,
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length: 10,
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bus: 0,
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source: 4,
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gsi: 4,
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flags: 0,
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});
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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// MCFG
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let mut mcfg = SDT::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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mcfg.append(0u64);
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// 32-bit PCI enhanced configuration mechanism
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mcfg.append(PCIRangeEntry {
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base_address: layout::MEM_32BIT_DEVICES_START.0,
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segment: 0,
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start: 0,
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end: 0xff,
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..Default::default()
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});
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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// XSDT
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let mut xsdt = SDT::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
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for table in tables {
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xsdt.append(table);
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}
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xsdt.update_checksum();
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let xsdt_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(xsdt.as_slice(), xsdt_offset)
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.expect("Error writing XSDT table");
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// RSDP
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let rsdp = RSDP::new(*b"CLOUDH", xsdt_offset.0);
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guest_mem
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.write_slice(rsdp.as_slice(), rsdp_offset)
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.expect("Error writing RSDP");
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rsdp_offset
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}
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