mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2026-08-05 02:19:16 +00:00
e4bb6409ae
Before this change, the FDT was loaded at the end of RAM. The address of FDT was not fixed. While UEFI (edk2 now) requires fixed address to find FDT and RSDP. Now the FDT is moved to the beginning of RAM, which is a fixed address. RSDP is wrote to 2 MiB after FDT, also a fixed address. Kernel comes 2 MiB after RSDP. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
305 lines
8.9 KiB
Rust
305 lines
8.9 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use crate::cpu::CpuManager;
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use crate::device_manager::DeviceManager;
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use crate::memory_manager::MemoryManager;
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use crate::vm::NumaNodes;
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#[cfg(target_arch = "x86_64")]
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use acpi_tables::sdt::GenericAddress;
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use acpi_tables::{aml::Aml, rsdp::Rsdp, sdt::Sdt};
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use bitflags::bitflags;
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use std::sync::{Arc, Mutex};
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use vm_memory::GuestRegionMmap;
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use vm_memory::{Address, ByteValued, Bytes, GuestAddress, GuestMemoryMmap, GuestMemoryRegion};
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#[repr(packed)]
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#[derive(Default)]
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struct PciRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct MemoryAffinity {
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pub type_: u8,
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pub length: u8,
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pub proximity_domain: u32,
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_reserved1: u16,
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pub base_addr_lo: u32,
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pub base_addr_hi: u32,
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pub length_lo: u32,
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pub length_hi: u32,
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_reserved2: u32,
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pub flags: u32,
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_reserved3: u64,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct ProcessorLocalX2ApicAffinity {
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pub type_: u8,
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pub length: u8,
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_reserved1: u16,
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pub proximity_domain: u32,
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pub x2apic_id: u32,
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pub flags: u32,
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pub clock_domain: u32,
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_reserved2: u32,
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}
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bitflags! {
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pub struct MemAffinityFlags: u32 {
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const NOFLAGS = 0;
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const ENABLE = 0b1;
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const HOTPLUGGABLE = 0b10;
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const NON_VOLATILE = 0b100;
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}
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}
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impl MemoryAffinity {
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fn from_region(
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region: &Arc<GuestRegionMmap>,
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proximity_domain: u32,
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flags: MemAffinityFlags,
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) -> Self {
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let base_addr = region.start_addr().raw_value();
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let base_addr_lo = (base_addr & 0xffff_ffff) as u32;
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let base_addr_hi = (base_addr >> 32) as u32;
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let length = region.len() as u64;
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let length_lo = (length & 0xffff_ffff) as u32;
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let length_hi = (length >> 32) as u32;
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MemoryAffinity {
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type_: 1,
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length: 40,
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proximity_domain,
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base_addr_lo,
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base_addr_hi,
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length_lo,
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length_hi,
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flags: flags.bits(),
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..Default::default()
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}
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}
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}
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pub fn create_dsdt_table(
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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) -> Sdt {
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// DSDT
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let mut dsdt = Sdt::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append_slice(device_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt.append_slice(cpu_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt.append_slice(memory_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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numa_nodes: &NumaNodes,
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) -> GuestAddress {
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let rsdp_offset = arch::layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager);
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let dsdt_offset = rsdp_offset.checked_add(Rsdp::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = Sdt::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// PM_TMR_BLK I/O port
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#[cfg(target_arch = "x86_64")]
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facp.write(76, 0xb008u32);
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// HW_REDUCED_ACPI, RESET_REG_SUP, TMR_VAL_EXT
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let fadt_flags: u32 = 1 << 20 | 1 << 10 | 1 << 8;
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facp.write(112, fadt_flags);
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// RESET_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(116, GenericAddress::io_port_address::<u8>(0x3c0));
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// RESET_VALUE
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#[cfg(target_arch = "x86_64")]
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// X_PM_TMR_BLK
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#[cfg(target_arch = "x86_64")]
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facp.write(208, GenericAddress::io_port_address::<u32>(0xb008));
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// SLEEP_CONTROL_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(244, GenericAddress::io_port_address::<u8>(0x3c0));
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// SLEEP_STATUS_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(256, GenericAddress::io_port_address::<u8>(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let madt = cpu_manager.lock().unwrap().create_madt();
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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// MCFG
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let mut mcfg = Sdt::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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mcfg.append(0u64);
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// 32-bit PCI enhanced configuration mechanism
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mcfg.append(PciRangeEntry {
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base_address: arch::layout::PCI_MMCONFIG_START.0,
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segment: 0,
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start: 0,
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end: 0,
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..Default::default()
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});
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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// SRAT and SLIT
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// Only created if the NUMA nodes list is not empty.
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let (prev_tbl_len, prev_tbl_off) = if numa_nodes.is_empty() {
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(mcfg.len(), mcfg_offset)
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} else {
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// SRAT
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let mut srat = Sdt::new(*b"SRAT", 36, 3, *b"CLOUDH", *b"CHSRAT ", 1);
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// SRAT reserved 12 bytes
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srat.append_slice(&[0u8; 12]);
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// Check the MemoryAffinity structure is the right size as expected by
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// the ACPI specification.
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assert_eq!(std::mem::size_of::<MemoryAffinity>(), 40);
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for (node_id, node) in numa_nodes.iter() {
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let proximity_domain = *node_id as u32;
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for region in node.memory_regions() {
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srat.append(MemoryAffinity::from_region(
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region,
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proximity_domain,
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MemAffinityFlags::ENABLE,
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))
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}
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for region in node.hotplug_regions() {
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srat.append(MemoryAffinity::from_region(
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region,
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proximity_domain,
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MemAffinityFlags::ENABLE | MemAffinityFlags::HOTPLUGGABLE,
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))
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}
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for cpu in node.cpus() {
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let x2apic_id = *cpu as u32;
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// Flags
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// - Enabled = 1 (bit 0)
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// - Reserved bits 1-31
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let flags = 1;
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srat.append(ProcessorLocalX2ApicAffinity {
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type_: 2,
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length: 24,
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proximity_domain,
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x2apic_id,
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flags,
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clock_domain: 0,
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..Default::default()
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});
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}
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}
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let srat_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(srat.as_slice(), srat_offset)
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.expect("Error writing SRAT table");
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tables.push(srat_offset.0);
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// SLIT
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let mut slit = Sdt::new(*b"SLIT", 36, 1, *b"CLOUDH", *b"CHSLIT ", 1);
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// Number of System Localities on 8 bytes.
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slit.append(numa_nodes.len() as u64);
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let existing_nodes: Vec<u32> = numa_nodes.keys().cloned().collect();
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for (node_id, node) in numa_nodes.iter() {
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let distances = node.distances();
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for i in existing_nodes.iter() {
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let dist: u8 = if *node_id == *i {
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10
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} else if let Some(distance) = distances.get(i) {
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*distance as u8
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} else {
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20
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};
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slit.append(dist);
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}
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}
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let slit_offset = srat_offset.checked_add(srat.len() as u64).unwrap();
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guest_mem
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.write_slice(slit.as_slice(), slit_offset)
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.expect("Error writing SRAT table");
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tables.push(slit_offset.0);
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(slit.len(), slit_offset)
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};
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// XSDT
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let mut xsdt = Sdt::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
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for table in tables {
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xsdt.append(table);
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}
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xsdt.update_checksum();
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let xsdt_offset = prev_tbl_off.checked_add(prev_tbl_len as u64).unwrap();
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guest_mem
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.write_slice(xsdt.as_slice(), xsdt_offset)
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.expect("Error writing XSDT table");
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// RSDP
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let rsdp = Rsdp::new(*b"CLOUDH", xsdt_offset.0);
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guest_mem
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.write_slice(rsdp.as_slice(), rsdp_offset)
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.expect("Error writing RSDP");
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rsdp_offset
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}
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