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35 lines
833 B
Rust
35 lines
833 B
Rust
//
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// Copyright © 2020 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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// EFER (technically not a register) bits
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pub const EFER_LMA: u64 = 0x400;
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pub const EFER_LME: u64 = 0x100;
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// CR0 bits
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pub const CR0_PE: u64 = 0x1;
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pub const CR0_PG: u64 = 0x80000000;
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// CR4 bits
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pub const CR4_PAE: u64 = 0x20;
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pub const CR4_LA57: u64 = 0x1000;
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// RFlags bits
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pub const CF_SHIFT: usize = 0;
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pub const PF_SHIFT: usize = 2;
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pub const AF_SHIFT: usize = 4;
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pub const ZF_SHIFT: usize = 6;
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pub const SF_SHIFT: usize = 7;
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pub const DF_SHIFT: usize = 10;
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pub const OF_SHIFT: usize = 11;
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pub const CF: u64 = 1 << CF_SHIFT;
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pub const PF: u64 = 1 << PF_SHIFT;
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pub const AF: u64 = 1 << AF_SHIFT;
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pub const ZF: u64 = 1 << ZF_SHIFT;
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pub const SF: u64 = 1 << SF_SHIFT;
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pub const DF: u64 = 1 << DF_SHIFT;
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pub const OF: u64 = 1 << OF_SHIFT;
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