mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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66a31c19e8
Call the "CTFY" method that will itself call Notify() on the CPU objects in the ACPI namespace. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
617 lines
19 KiB
Rust
617 lines
19 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use acpi_tables::{
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aml,
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aml::Aml,
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rsdp::RSDP,
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sdt::{GenericAddress, SDT},
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};
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use vm_memory::{GuestAddress, GuestMemoryMmap};
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use vm_memory::{Address, ByteValued, Bytes};
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use std::convert::TryInto;
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use arch::layout;
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#[repr(packed)]
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struct LocalAPIC {
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pub r#type: u8,
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pub length: u8,
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pub processor_id: u8,
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pub apic_id: u8,
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pub flags: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IOAPIC {
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pub r#type: u8,
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pub length: u8,
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pub ioapic_id: u8,
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_reserved: u8,
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pub apic_address: u32,
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pub gsi_base: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct InterruptSourceOverride {
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pub r#type: u8,
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pub length: u8,
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pub bus: u8,
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pub source: u8,
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pub gsi: u32,
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pub flags: u16,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct PCIRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortParavirtIommuNode {
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pub type_: u8,
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pub length: u16,
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pub revision: u8,
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_reserved1: u32,
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pub num_id_mappings: u32,
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pub ref_id_mappings: u32,
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pub device_id: u32,
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_reserved2: [u32; 3],
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pub model: u32,
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pub flags: u32,
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_reserved3: [u32; 4],
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortPciRootComplexNode {
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pub type_: u8,
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pub length: u16,
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pub revision: u8,
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_reserved1: u32,
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pub num_id_mappings: u32,
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pub ref_id_mappings: u32,
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pub mem_access_props: IortMemoryAccessProperties,
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pub ats_attr: u32,
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pub pci_seg_num: u32,
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pub mem_addr_size_limit: u8,
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_reserved2: [u8; 3],
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortMemoryAccessProperties {
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pub cca: u32,
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pub ah: u8,
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_reserved: u16,
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pub maf: u8,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortIdMapping {
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pub input_base: u32,
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pub num_of_ids: u32,
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pub ouput_base: u32,
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pub output_ref: u32,
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pub flags: u32,
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}
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struct CPU {
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cpu_id: u8,
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}
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const MADT_CPU_ENABLE_FLAG: usize = 0;
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impl aml::Aml for CPU {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let lapic = LocalAPIC {
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r#type: 0,
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length: 8,
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processor_id: self.cpu_id,
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apic_id: self.cpu_id,
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flags: 1 << MADT_CPU_ENABLE_FLAG,
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};
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let mut mat_data: Vec<u8> = Vec::new();
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mat_data.resize(std::mem::size_of_val(&lapic), 0);
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unsafe { *(mat_data.as_mut_ptr() as *mut LocalAPIC) = lapic };
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aml::Device::new(
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format!("C{:03}", self.cpu_id).as_str().into(),
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vec![
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&aml::Name::new("_HID".into(), &"ACPI0007"),
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&aml::Name::new("_UID".into(), &self.cpu_id),
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/*
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_STA return value:
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Bit [0] – Set if the device is present.
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Bit [1] – Set if the device is enabled and decoding its resources.
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Bit [2] – Set if the device should be shown in the UI.
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Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
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Bit [4] – Set if the battery is present.
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Bits [31:5] – Reserved (must be cleared).
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*/
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&aml::Method::new(
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"_STA".into(),
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0,
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false,
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// Call into CSTA method which will interrogate device
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vec![&aml::Return::new(&aml::MethodCall::new(
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"CSTA".into(),
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vec![&self.cpu_id],
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))],
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),
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// The Linux kernel expects every CPU device to have a _MAT entry
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// containing the LAPIC for this processor with the enabled bit set
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// even it if is disabled in the MADT (non-boot CPU)
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&aml::Name::new("_MAT".into(), &aml::Buffer::new(mat_data)),
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],
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)
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.to_aml_bytes()
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}
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}
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struct CPUMethods {
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max_vcpus: u8,
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}
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impl Aml for CPUMethods {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let mut bytes = Vec::new();
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bytes.extend_from_slice(
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// CPU status method
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&aml::Method::new(
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"CSTA".into(),
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1,
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true,
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xfff),
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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// Check if CPEN bit is set, if so make the local variable 0xf (see _STA for details of meaning)
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CPEN"), &aml::ONE),
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vec![&aml::Store::new(&aml::Local(0), &0xfu8)],
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),
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// Release lock
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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// Return 0 or 0xf
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&aml::Return::new(&aml::Local(0)),
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],
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)
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.to_aml_bytes(),
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);
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let mut paths = Vec::new();
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for cpu_id in 0..self.max_vcpus {
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paths.push(aml::Path::new(format!("C{:03}", cpu_id).as_str()))
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}
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let mut notify_methods = Vec::new();
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for cpu_id in 0..self.max_vcpus {
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notify_methods.push(aml::Notify::new(&paths[usize::from(cpu_id)], &aml::ONE));
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}
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let mut notify_methods_inner: Vec<&dyn Aml> = Vec::new();
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for notify_method in notify_methods.iter() {
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notify_methods_inner.push(notify_method);
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}
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bytes.extend_from_slice(
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// Notify all vCPUs
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&aml::Method::new("CTFY".into(), 0, true, notify_methods_inner).to_aml_bytes(),
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);
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bytes
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}
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}
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fn create_cpu_data(max_vcpus: u8) -> Vec<u8> {
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let mut bytes = Vec::new();
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// CPU hotplug controller
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bytes.extend_from_slice(
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&aml::Device::new(
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"_SB_.PRES".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0A06")),
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// Mutex to protect concurrent access as we write to choose CPU and then read back status
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&aml::Mutex::new("CPLK".into(), 0),
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// I/O port for CPU controller
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::IO::new(0x0cd8, 0x0cd8, 0x01, 0x0c)]),
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),
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// OpRegion and Fields map I/O port into individual field values
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&aml::OpRegion::new("PRST".into(), aml::OpRegionSpace::SystemIO, 0x0cd8, 0x0c),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::Byte,
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aml::FieldUpdateRule::WriteAsZeroes,
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vec![
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CPEN", 1),
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aml::FieldEntry::Named(*b"CINS", 1),
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aml::FieldEntry::Named(*b"CRMV", 1),
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aml::FieldEntry::Named(*b"CEJ0", 1),
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aml::FieldEntry::Reserved(4),
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aml::FieldEntry::Named(*b"CCMD", 8),
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],
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),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::DWord,
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aml::FieldUpdateRule::Preserve,
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vec![
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aml::FieldEntry::Named(*b"CSEL", 32),
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CDAT", 32),
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],
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),
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],
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)
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.to_aml_bytes(),
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);
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// CPU devices
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let hid = aml::Name::new("_HID".into(), &"ACPI0010");
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let uid = aml::Name::new("_CID".into(), &aml::EISAName::new("PNP0A05"));
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// Bundle methods together under a common object
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let methods = CPUMethods { max_vcpus };
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let mut cpu_data_inner: Vec<&dyn aml::Aml> = vec![&hid, &uid, &methods];
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let mut cpu_devices = Vec::new();
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for cpu_id in 0..max_vcpus {
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let cpu_device = CPU { cpu_id };
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cpu_devices.push(cpu_device);
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}
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for cpu_device in cpu_devices.iter() {
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cpu_data_inner.push(cpu_device);
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}
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bytes.extend_from_slice(&aml::Device::new("_SB_.CPUS".into(), cpu_data_inner).to_aml_bytes());
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bytes
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}
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fn create_ged_device() -> Vec<u8> {
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aml::Device::new(
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"_SB_.GED_".into(),
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vec![
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&aml::Name::new("_HID".into(), &"ACPI0013"),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::Interrupt::new(
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true, false, false, false, 5,
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)]),
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),
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&aml::OpRegion::new("GDST".into(), aml::OpRegionSpace::SystemIO, 0xb000, 0x1),
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&aml::Field::new(
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"GDST".into(),
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aml::FieldAccessType::Byte,
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aml::FieldUpdateRule::WriteAsZeroes,
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vec![aml::FieldEntry::Named(*b"GDAT", 8)],
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),
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&aml::Method::new(
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"_EVT".into(),
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1,
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true,
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vec![&aml::If::new(
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&aml::Equal::new(&aml::Path::new("GDAT"), &aml::ONE),
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vec![&aml::MethodCall::new("\\_SB_.CPUS.CTFY".into(), vec![])],
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)],
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),
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],
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)
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.to_aml_bytes()
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}
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pub fn create_dsdt_table(
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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max_vcpus: u8,
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) -> SDT {
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let pci_dsdt_data = aml::Device::new(
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"_SB_.PCI0".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0A08")),
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&aml::Name::new("_CID".into(), &aml::EISAName::new("PNP0A03")),
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&aml::Name::new("_ADR".into(), &aml::ZERO),
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&aml::Name::new("_SEG".into(), &aml::ZERO),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new("SUPP".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0xffu16),
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&aml::IO::new(0xcf8, 0xcf8, 1, 0x8),
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&aml::AddressSpace::new_io(0x0u16, 0xcf7u16),
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&aml::AddressSpace::new_io(0xd00u16, 0xffffu16),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1)
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as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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start_of_device_area.0,
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end_of_device_area.0,
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),
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]),
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),
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],
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)
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.to_aml_bytes();
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let mbrd_dsdt_data = aml::Device::new(
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"_SB_.MBRD".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0C02")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::Memory32Fixed::new(
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true,
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layout::PCI_MMCONFIG_START.0 as u32,
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layout::PCI_MMCONFIG_SIZE as u32,
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)]),
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),
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],
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)
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.to_aml_bytes();
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let com1_dsdt_data = aml::Device::new(
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"_SB_.COM1".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0501")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::Interrupt::new(true, true, false, false, 4),
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&aml::IO::new(0x3f8, 0x3f8, 0, 0x8),
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]),
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),
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],
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)
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.to_aml_bytes();
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let s5_sleep_data =
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aml::Name::new("_S5_".into(), &aml::Package::new(vec![&5u8])).to_aml_bytes();
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let cpu_data = create_cpu_data(max_vcpus);
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let ged_data = create_ged_device();
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// DSDT
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let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append_slice(pci_dsdt_data.as_slice());
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dsdt.append_slice(mbrd_dsdt_data.as_slice());
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if serial_enabled {
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dsdt.append_slice(com1_dsdt_data.as_slice());
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}
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dsdt.append_slice(s5_sleep_data.as_slice());
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dsdt.append_slice(cpu_data.as_slice());
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dsdt.append_slice(ged_data.as_slice());
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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boot_vcpus: u8,
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max_vcpus: u8,
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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virt_iommu: Option<(u32, &[u32])>,
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) -> GuestAddress {
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// RSDP is at the EBDA
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let rsdp_offset = layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(
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serial_enabled,
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start_of_device_area,
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end_of_device_area,
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max_vcpus,
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);
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let dsdt_offset = rsdp_offset.checked_add(RSDP::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = SDT::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// HW_REDUCED_ACPI and RESET_REG_SUP
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let fadt_flags: u32 = 1 << 20 | 1 << 10;
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facp.write(112, fadt_flags);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let mut madt = SDT::new(*b"APIC", 44, 5, *b"CLOUDH", *b"CHMADT ", 1);
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madt.write(36, layout::APIC_START);
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// This is also checked in the commandline parsing.
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assert!(boot_vcpus <= max_vcpus);
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for cpu in 0..max_vcpus {
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let lapic = LocalAPIC {
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r#type: 0,
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length: 8,
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processor_id: cpu,
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apic_id: cpu,
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flags: if cpu < boot_vcpus {
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1 << MADT_CPU_ENABLE_FLAG
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} else {
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0
|
||
},
|
||
};
|
||
madt.append(lapic);
|
||
}
|
||
|
||
madt.append(IOAPIC {
|
||
r#type: 1,
|
||
length: 12,
|
||
ioapic_id: 0,
|
||
apic_address: layout::IOAPIC_START.0 as u32,
|
||
gsi_base: 0,
|
||
..Default::default()
|
||
});
|
||
|
||
madt.append(InterruptSourceOverride {
|
||
r#type: 2,
|
||
length: 10,
|
||
bus: 0,
|
||
source: 4,
|
||
gsi: 4,
|
||
flags: 0,
|
||
});
|
||
|
||
let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
|
||
guest_mem
|
||
.write_slice(madt.as_slice(), madt_offset)
|
||
.expect("Error writing MADT table");
|
||
tables.push(madt_offset.0);
|
||
|
||
// MCFG
|
||
let mut mcfg = SDT::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
|
||
|
||
// MCFG reserved 8 bytes
|
||
mcfg.append(0u64);
|
||
|
||
// 32-bit PCI enhanced configuration mechanism
|
||
mcfg.append(PCIRangeEntry {
|
||
base_address: layout::PCI_MMCONFIG_START.0,
|
||
segment: 0,
|
||
start: 0,
|
||
end: 0xff,
|
||
..Default::default()
|
||
});
|
||
|
||
let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
|
||
guest_mem
|
||
.write_slice(mcfg.as_slice(), mcfg_offset)
|
||
.expect("Error writing MCFG table");
|
||
tables.push(mcfg_offset.0);
|
||
|
||
let (prev_tbl_len, prev_tbl_off) = if let Some((iommu_id, dev_ids)) = &virt_iommu {
|
||
// IORT
|
||
let mut iort = SDT::new(*b"IORT", 36, 1, *b"CLOUDH", *b"CHIORT ", 1);
|
||
// IORT number of nodes
|
||
iort.append(2u32);
|
||
// IORT offset to array of IORT nodes
|
||
iort.append(48u32);
|
||
// IORT reserved 4 bytes
|
||
iort.append(0u32);
|
||
// IORT paravirtualized IOMMU node
|
||
iort.append(IortParavirtIommuNode {
|
||
type_: 128,
|
||
length: 56,
|
||
revision: 0,
|
||
num_id_mappings: 0,
|
||
ref_id_mappings: 56,
|
||
device_id: *iommu_id,
|
||
model: 1,
|
||
..Default::default()
|
||
});
|
||
|
||
let num_entries = dev_ids.len();
|
||
let length: u16 = (36 + (20 * num_entries)).try_into().unwrap();
|
||
|
||
// IORT PCI root complex node
|
||
iort.append(IortPciRootComplexNode {
|
||
type_: 2,
|
||
length,
|
||
revision: 0,
|
||
num_id_mappings: num_entries as u32,
|
||
ref_id_mappings: 36,
|
||
ats_attr: 0,
|
||
pci_seg_num: 0,
|
||
mem_addr_size_limit: 255,
|
||
..Default::default()
|
||
});
|
||
|
||
for dev_id in dev_ids.iter() {
|
||
// IORT ID mapping
|
||
iort.append(IortIdMapping {
|
||
input_base: *dev_id,
|
||
num_of_ids: 1,
|
||
ouput_base: *dev_id,
|
||
output_ref: 48,
|
||
flags: 0,
|
||
});
|
||
}
|
||
|
||
let iort_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
|
||
guest_mem
|
||
.write_slice(iort.as_slice(), iort_offset)
|
||
.expect("Error writing IORT table");
|
||
tables.push(iort_offset.0);
|
||
|
||
(iort.len(), iort_offset)
|
||
} else {
|
||
(mcfg.len(), mcfg_offset)
|
||
};
|
||
|
||
// XSDT
|
||
let mut xsdt = SDT::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
|
||
for table in tables {
|
||
xsdt.append(table);
|
||
}
|
||
xsdt.update_checksum();
|
||
|
||
let xsdt_offset = prev_tbl_off.checked_add(prev_tbl_len as u64).unwrap();
|
||
guest_mem
|
||
.write_slice(xsdt.as_slice(), xsdt_offset)
|
||
.expect("Error writing XSDT table");
|
||
|
||
// RSDP
|
||
let rsdp = RSDP::new(*b"CLOUDH", xsdt_offset.0);
|
||
guest_mem
|
||
.write_slice(rsdp.as_slice(), rsdp_offset)
|
||
.expect("Error writing RSDP");
|
||
|
||
rsdp_offset
|
||
}
|