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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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fcfae4cc4b
config_generation is a u8 and the spec mandates wrap around. Verify the increment past 0xff lands on 0x00 without panicking under overflow checks. Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
644 lines
24 KiB
Rust
644 lines
24 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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//
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// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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use std::sync::atomic::{AtomicBool, AtomicU8, AtomicU16, Ordering};
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use std::sync::{Arc, Mutex};
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use byteorder::{ByteOrder, LittleEndian};
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use log::{debug, error, warn};
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use serde::{Deserialize, Serialize};
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use virtio_queue::{Queue, QueueT};
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use vm_migration::{MigratableError, Pausable, Snapshot, Snapshottable};
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use super::pci_device::VIRTQ_MSI_NO_VECTOR;
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use crate::VirtioDevice;
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pub const VIRTIO_PCI_COMMON_CONFIG_ID: &str = "virtio_pci_common_config";
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#[derive(Clone, Serialize, Deserialize)]
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pub struct VirtioPciCommonConfigState {
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pub driver_status: u8,
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pub config_generation: u8,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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pub msix_config: u16,
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pub msix_queues: Vec<u16>,
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}
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/* The standard layout for the ring is a continuous chunk of memory which looks
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* like this. We assume num is a power of 2.
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*
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* struct vring
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* {
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* // The actual descriptors (16 bytes each)
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* struct vring_desc desc[num];
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*
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* // A ring of available descriptor heads with free-running index.
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* __virtio16 avail_flags;
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* __virtio16 avail_idx;
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* __virtio16 available[num];
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* __virtio16 used_event_idx;
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*
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* // Padding to the next align boundary.
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* char pad[];
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*
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* // A ring of used descriptor heads with free-running index.
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* __virtio16 used_flags;
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* __virtio16 used_idx;
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* struct vring_used_elem used[num];
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* __virtio16 avail_event_idx;
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* };
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* struct vring_desc {
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* __virtio64 addr;
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* __virtio32 len;
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* __virtio16 flags;
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* __virtio16 next;
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* };
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*
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* struct vring_avail {
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* __virtio16 flags;
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* __virtio16 idx;
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* __virtio16 ring[];
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* };
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*
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* // u32 is used here for ids for padding reasons.
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* struct vring_used_elem {
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* // Index of start of used descriptor chain.
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* __virtio32 id;
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* // Total length of the descriptor chain which was used (written to)
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* __virtio32 len;
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* };
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*
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* Kernel header used for this reference: include/uapi/linux/virtio_ring.h
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* Virtio Spec: https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html
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*
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*/
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const VRING_DESC_ELEMENT_SIZE: usize = 16;
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const VRING_AVAIL_ELEMENT_SIZE: usize = 2;
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const VRING_USED_ELEMENT_SIZE: usize = 8;
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#[derive(Copy, Clone)]
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pub enum VringType {
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Desc,
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Avail,
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Used,
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}
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pub fn get_vring_size(t: VringType, queue_size: u16) -> u64 {
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let (length_except_ring, element_size) = match t {
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VringType::Desc => (0, VRING_DESC_ELEMENT_SIZE),
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VringType::Avail => (6, VRING_AVAIL_ELEMENT_SIZE),
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VringType::Used => (6, VRING_USED_ELEMENT_SIZE),
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};
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(length_except_ring + element_size * queue_size as usize) as u64
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}
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/// Contains the data for reading and writing the common configuration structure of a virtio PCI
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/// device.
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///
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/// * Registers:
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///
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/// ** About the whole device.
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/// le32 device_feature_select; // 0x00 // read-write
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/// le32 device_feature; // 0x04 // read-only for driver
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/// le32 driver_feature_select; // 0x08 // read-write
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/// le32 driver_feature; // 0x0C // read-write
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/// le16 msix_config; // 0x10 // read-write
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/// le16 num_queues; // 0x12 // read-only for driver
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/// u8 device_status; // 0x14 // read-write (driver_status)
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/// u8 config_generation; // 0x15 // read-only for driver
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///
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/// ** About a specific virtqueue.
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/// le16 queue_select; // 0x16 // read-write
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/// le16 queue_size; // 0x18 // read-write, power of 2, or 0.
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/// le16 queue_msix_vector; // 0x1A // read-write
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/// le16 queue_enable; // 0x1C // read-write (Ready)
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/// le16 queue_notify_off; // 0x1E // read-only for driver
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/// le64 queue_desc; // 0x20 // read-write
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/// le64 queue_avail; // 0x28 // read-write
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/// le64 queue_used; // 0x30 // read-write
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pub struct VirtioPciCommonConfig {
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pub device: Arc<Mutex<dyn VirtioDevice>>,
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pub driver_status: Arc<AtomicU8>,
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pub config_generation: Arc<AtomicU8>,
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/// Set when a Config interrupt fires. Cleared on the next read of
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/// the device specific configuration region, which also bumps
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/// config_generation.
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pub config_changed: Arc<AtomicBool>,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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pub msix_config: Arc<AtomicU16>,
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pub msix_queues: Arc<Mutex<Vec<u16>>>,
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}
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impl VirtioPciCommonConfig {
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pub fn new(state: VirtioPciCommonConfigState, device: Arc<Mutex<dyn VirtioDevice>>) -> Self {
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VirtioPciCommonConfig {
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device,
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driver_status: Arc::new(AtomicU8::new(state.driver_status)),
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config_generation: Arc::new(AtomicU8::new(state.config_generation)),
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config_changed: Arc::new(AtomicBool::new(false)),
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device_feature_select: state.device_feature_select,
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driver_feature_select: state.driver_feature_select,
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queue_select: state.queue_select,
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msix_config: Arc::new(AtomicU16::new(state.msix_config)),
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msix_queues: Arc::new(Mutex::new(state.msix_queues)),
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}
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}
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/// If a Config interrupt has fired since the last device specific
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/// configuration read, increment config_generation and clear the
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/// pending flag.
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pub fn consume_config_change(&self) {
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if self.config_changed.swap(false, Ordering::AcqRel) {
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// Wrap at u8 max is intentional per the virtio spec.
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self.config_generation.fetch_add(1, Ordering::Release);
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}
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}
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fn state(&self) -> VirtioPciCommonConfigState {
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VirtioPciCommonConfigState {
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driver_status: self.driver_status.load(Ordering::Acquire),
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config_generation: self.config_generation.load(Ordering::Acquire),
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device_feature_select: self.device_feature_select,
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driver_feature_select: self.driver_feature_select,
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queue_select: self.queue_select,
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msix_config: self.msix_config.load(Ordering::Acquire),
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msix_queues: self.msix_queues.lock().unwrap().clone(),
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}
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}
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/// Returns the common configuration to its power-on state. Per the virtio
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/// spec a device reset must restore the values that a fresh driver would
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/// observe.
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pub fn reset(&mut self) {
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self.driver_status.store(0, Ordering::Release);
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self.config_changed.store(false, Ordering::Release);
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self.device_feature_select = 0;
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self.driver_feature_select = 0;
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self.queue_select = 0;
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self.msix_config
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.store(VIRTQ_MSI_NO_VECTOR, Ordering::Release);
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self.msix_queues.lock().unwrap().fill(VIRTQ_MSI_NO_VECTOR);
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}
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pub fn read(&mut self, offset: u64, data: &mut [u8], queues: &[Queue]) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => {
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let v = self.read_common_config_byte(offset);
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data[0] = v;
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}
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2 => {
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let v = self.read_common_config_word(offset, queues);
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LittleEndian::write_u16(data, v);
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}
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4 => {
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let v = self.read_common_config_dword(offset);
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LittleEndian::write_u32(data, v);
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}
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8 => {
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let v = self.read_common_config_qword(offset);
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LittleEndian::write_u64(data, v);
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}
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_ => error!("invalid data length for virtio read: len {}", data.len()),
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}
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}
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pub fn write(&mut self, offset: u64, data: &[u8], queues: &mut [Queue]) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => self.write_common_config_byte(offset, data[0]),
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2 => self.write_common_config_word(offset, LittleEndian::read_u16(data), queues),
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4 => {
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self.write_common_config_dword(offset, LittleEndian::read_u32(data), queues);
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}
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8 => self.write_common_config_qword(offset, LittleEndian::read_u64(data), queues),
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_ => error!("invalid data length for virtio write: len {}", data.len()),
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}
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}
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fn read_common_config_byte(&self, offset: u64) -> u8 {
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debug!("read_common_config_byte: offset 0x{offset:x}");
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// The driver is only allowed to do aligned, properly sized access.
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match offset {
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0x14 => self.driver_status.load(Ordering::Acquire),
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0x15 => self.config_generation.load(Ordering::Acquire),
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_ => {
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warn!("invalid virtio config byte read: 0x{offset:x}");
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0
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}
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}
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}
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fn write_common_config_byte(&mut self, offset: u64, value: u8) {
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debug!("write_common_config_byte: offset 0x{offset:x}");
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match offset {
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0x14 => self.driver_status.store(value, Ordering::Release),
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_ => {
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warn!("invalid virtio config byte write: 0x{offset:x}");
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}
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}
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}
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fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
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debug!("read_common_config_word: offset 0x{offset:x}");
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match offset {
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0x10 => self.msix_config.load(Ordering::Acquire),
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0x12 => queues.len() as u16, // num_queues
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0x16 => self.queue_select,
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0x18 => self.with_queue(queues, |q| q.size()).unwrap_or(0),
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0x1a => self
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.msix_queues
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.lock()
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.unwrap()
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.get(usize::from(self.queue_select))
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.copied()
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.unwrap_or(VIRTQ_MSI_NO_VECTOR),
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0x1c => u16::from(self.with_queue(queues, |q| q.ready()).unwrap_or(false)),
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0x1e => self.queue_select, // notify_off
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_ => {
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warn!("invalid virtio register word read: 0x{offset:x}");
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0
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}
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}
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}
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fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) {
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debug!("write_common_config_word: offset 0x{offset:x}");
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match offset {
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0x10 => self.msix_config.store(value, Ordering::Release),
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0x16 => self.queue_select = value,
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0x18 => self.with_queue_mut(queues, |q| q.set_size(value)),
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0x1a => {
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if let Some(entry) = self
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.msix_queues
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.lock()
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.unwrap()
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.get_mut(usize::from(self.queue_select))
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{
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*entry = value;
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}
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}
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0x1c => self.with_queue_mut(queues, |q| {
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let ready = value == 1;
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q.set_ready(ready);
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let access_platform = if ready {
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self.device.lock().unwrap().access_platform()
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} else {
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None
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};
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if let Some(access_platform) = access_platform {
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let desc_table = match access_platform
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.translate_gva(q.desc_table(), get_vring_size(VringType::Desc, q.size()))
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{
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Ok(addr) => addr,
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Err(e) => {
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error!("Failed to translate desc_table GVA: {e}");
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q.set_ready(false);
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return;
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}
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};
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let avail_ring = match access_platform
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.translate_gva(q.avail_ring(), get_vring_size(VringType::Avail, q.size()))
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{
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Ok(addr) => addr,
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Err(e) => {
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error!("Failed to translate avail_ring GVA: {e}");
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q.set_ready(false);
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return;
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}
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};
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let used_ring = match access_platform
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.translate_gva(q.used_ring(), get_vring_size(VringType::Used, q.size()))
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{
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Ok(addr) => addr,
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Err(e) => {
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error!("Failed to translate used_ring GVA: {e}");
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q.set_ready(false);
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return;
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}
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};
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q.set_desc_table_address(
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Some((desc_table & 0xffff_ffff) as u32),
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Some((desc_table >> 32) as u32),
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);
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q.set_avail_ring_address(
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Some((avail_ring & 0xffff_ffff) as u32),
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Some((avail_ring >> 32) as u32),
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);
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q.set_used_ring_address(
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Some((used_ring & 0xffff_ffff) as u32),
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Some((used_ring >> 32) as u32),
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);
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}
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}),
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_ => {
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warn!("invalid virtio register word write: 0x{offset:x}");
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}
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}
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}
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fn read_common_config_dword(&self, offset: u64) -> u32 {
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debug!("read_common_config_dword: offset 0x{offset:x}");
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match offset {
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0x00 => self.device_feature_select,
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0x04 => {
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let locked_device = self.device.lock().unwrap();
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if self.device_feature_select < 2 {
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(locked_device.features() >> (self.device_feature_select * 32)) as u32
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} else {
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0
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}
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}
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0x08 => self.driver_feature_select,
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_ => {
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warn!("invalid virtio register dword read: 0x{offset:x}");
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0
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}
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}
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}
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fn write_common_config_dword(&mut self, offset: u64, value: u32, queues: &mut [Queue]) {
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debug!("write_common_config_dword: offset 0x{offset:x}");
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match offset {
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0x00 => self.device_feature_select = value,
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0x08 => self.driver_feature_select = value,
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0x0c => {
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if self.driver_feature_select < 2 {
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let mut locked_device = self.device.lock().unwrap();
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locked_device
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.ack_features(u64::from(value) << (self.driver_feature_select * 32));
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}
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}
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0x20 => self.with_queue_mut(queues, |q| q.set_desc_table_address(Some(value), None)),
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0x24 => self.with_queue_mut(queues, |q| q.set_desc_table_address(None, Some(value))),
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0x28 => self.with_queue_mut(queues, |q| q.set_avail_ring_address(Some(value), None)),
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0x2c => self.with_queue_mut(queues, |q| q.set_avail_ring_address(None, Some(value))),
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0x30 => self.with_queue_mut(queues, |q| q.set_used_ring_address(Some(value), None)),
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0x34 => self.with_queue_mut(queues, |q| q.set_used_ring_address(None, Some(value))),
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_ => {
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warn!("invalid virtio register dword write: 0x{offset:x}");
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}
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}
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}
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fn read_common_config_qword(&self, _offset: u64) -> u64 {
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debug!("read_common_config_qword: offset 0x{_offset:x}");
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0 // Assume the guest has no reason to read write-only registers.
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}
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fn write_common_config_qword(&mut self, offset: u64, value: u64, queues: &mut [Queue]) {
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debug!("write_common_config_qword: offset 0x{offset:x}");
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let low = Some((value & 0xffff_ffff) as u32);
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let high = Some((value >> 32) as u32);
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match offset {
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0x20 => self.with_queue_mut(queues, |q| q.set_desc_table_address(low, high)),
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0x28 => self.with_queue_mut(queues, |q| q.set_avail_ring_address(low, high)),
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0x30 => self.with_queue_mut(queues, |q| q.set_used_ring_address(low, high)),
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_ => {
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warn!("invalid virtio register qword write: 0x{offset:x}");
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}
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}
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}
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fn with_queue<U, F>(&self, queues: &[Queue], f: F) -> Option<U>
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where
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F: FnOnce(&Queue) -> U,
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{
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queues.get(self.queue_select as usize).map(f)
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}
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fn with_queue_mut<F: FnOnce(&mut Queue)>(&self, queues: &mut [Queue], f: F) {
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if let Some(queue) = queues.get_mut(self.queue_select as usize) {
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f(queue);
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}
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}
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}
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impl Pausable for VirtioPciCommonConfig {}
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impl Snapshottable for VirtioPciCommonConfig {
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fn id(&self) -> String {
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String::from(VIRTIO_PCI_COMMON_CONFIG_ID)
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}
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fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
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Snapshot::new_from_state(&self.state())
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}
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}
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#[cfg(test)]
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mod unit_tests {
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use super::*;
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use crate::{ActivateResult, ActivationContext};
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struct DummyDevice(u32);
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const QUEUE_SIZE: u16 = 256;
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const QUEUE_SIZES: &[u16] = &[QUEUE_SIZE];
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const DUMMY_FEATURES: u64 = 0x5555_aaaa;
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impl VirtioDevice for DummyDevice {
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fn device_type(&self) -> u32 {
|
|
self.0
|
|
}
|
|
fn queue_max_sizes(&self) -> &[u16] {
|
|
QUEUE_SIZES
|
|
}
|
|
fn activate(&mut self, _context: ActivationContext) -> ActivateResult {
|
|
Ok(())
|
|
}
|
|
|
|
fn features(&self) -> u64 {
|
|
DUMMY_FEATURES
|
|
}
|
|
|
|
fn ack_features(&mut self, _value: u64) {}
|
|
|
|
fn read_config(&self, _offset: u64, _data: &mut [u8]) {}
|
|
|
|
fn write_config(&mut self, _offset: u64, _data: &[u8]) {}
|
|
}
|
|
|
|
#[test]
|
|
fn write_base_regs() {
|
|
let dev: Arc<Mutex<dyn VirtioDevice>> = Arc::new(Mutex::new(DummyDevice(0)));
|
|
let mut regs = VirtioPciCommonConfig {
|
|
device: dev.clone(),
|
|
driver_status: Arc::new(AtomicU8::new(0xaa)),
|
|
config_generation: Arc::new(AtomicU8::new(0x55)),
|
|
config_changed: Arc::new(AtomicBool::new(false)),
|
|
device_feature_select: 0x0,
|
|
driver_feature_select: 0x0,
|
|
queue_select: 0xff,
|
|
msix_config: Arc::new(AtomicU16::new(0)),
|
|
msix_queues: Arc::new(Mutex::new(vec![0; 3])),
|
|
};
|
|
|
|
let mut queues = Vec::new();
|
|
|
|
// Can set all bits of driver_status.
|
|
regs.write(0x14, &[0x55], &mut queues);
|
|
let mut read_back = vec![0x00];
|
|
regs.read(0x14, &mut read_back, &queues);
|
|
assert_eq!(read_back[0], 0x55);
|
|
|
|
// The config generation register is read only.
|
|
regs.write(0x15, &[0xaa], &mut queues);
|
|
let mut read_back = vec![0x00];
|
|
regs.read(0x15, &mut read_back, &queues);
|
|
assert_eq!(read_back[0], 0x55);
|
|
|
|
// Device features is read-only and passed through from the device.
|
|
regs.write(0x04, &[0, 0, 0, 0], &mut queues);
|
|
let mut read_back = vec![0, 0, 0, 0];
|
|
regs.read(0x04, &mut read_back, &queues);
|
|
assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
|
|
|
|
// Feature select registers are read/write.
|
|
regs.write(0x00, &[1, 2, 3, 4], &mut queues);
|
|
let mut read_back = vec![0, 0, 0, 0];
|
|
regs.read(0x00, &mut read_back, &queues);
|
|
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
|
|
regs.write(0x08, &[1, 2, 3, 4], &mut queues);
|
|
let mut read_back = vec![0, 0, 0, 0];
|
|
regs.read(0x08, &mut read_back, &queues);
|
|
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
|
|
|
|
// 'queue_select' can be read and written.
|
|
regs.write(0x16, &[0xaa, 0x55], &mut queues);
|
|
let mut read_back = vec![0x00, 0x00];
|
|
regs.read(0x16, &mut read_back, &queues);
|
|
assert_eq!(read_back[0], 0xaa);
|
|
assert_eq!(read_back[1], 0x55);
|
|
}
|
|
|
|
#[test]
|
|
fn oob_queue_select_does_not_panic() {
|
|
let dev: Arc<Mutex<dyn VirtioDevice>> = Arc::new(Mutex::new(DummyDevice(0)));
|
|
let mut regs = VirtioPciCommonConfig {
|
|
device: dev.clone(),
|
|
driver_status: Arc::new(AtomicU8::new(0)),
|
|
config_generation: Arc::new(AtomicU8::new(0)),
|
|
config_changed: Arc::new(AtomicBool::new(false)),
|
|
device_feature_select: 0,
|
|
driver_feature_select: 0,
|
|
queue_select: 0,
|
|
msix_config: Arc::new(AtomicU16::new(0)),
|
|
msix_queues: Arc::new(Mutex::new(vec![0; 1])),
|
|
};
|
|
|
|
let mut queues = vec![Queue::new(256).unwrap()];
|
|
|
|
// Set queue_select to an out-of-bounds value.
|
|
regs.write(0x16, &[0xFF, 0xFF], &mut queues);
|
|
|
|
// Read queue_msix_vector — must not panic, should return VIRTQ_MSI_NO_VECTOR.
|
|
let mut read_back = vec![0x00, 0x00];
|
|
regs.read(0x1a, &mut read_back, &queues);
|
|
assert_eq!(LittleEndian::read_u16(&read_back), VIRTQ_MSI_NO_VECTOR);
|
|
|
|
// Write queue_msix_vector — must not panic.
|
|
regs.write(0x1a, &[0xAB, 0xCD], &mut queues);
|
|
}
|
|
|
|
#[test]
|
|
fn reset_returns_initial_state() {
|
|
let dev: Arc<Mutex<dyn VirtioDevice>> = Arc::new(Mutex::new(DummyDevice(0)));
|
|
let mut regs = VirtioPciCommonConfig {
|
|
device: dev,
|
|
driver_status: Arc::new(AtomicU8::new(0x55)),
|
|
config_generation: Arc::new(AtomicU8::new(0xab)),
|
|
config_changed: Arc::new(AtomicBool::new(true)),
|
|
device_feature_select: 1,
|
|
driver_feature_select: 1,
|
|
queue_select: 7,
|
|
msix_config: Arc::new(AtomicU16::new(3)),
|
|
msix_queues: Arc::new(Mutex::new(vec![1, 2, 3])),
|
|
};
|
|
|
|
regs.reset();
|
|
|
|
assert_eq!(regs.driver_status.load(Ordering::Acquire), 0);
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0xab); // unchanged across reset
|
|
assert!(!regs.config_changed.load(Ordering::Acquire));
|
|
assert_eq!(regs.device_feature_select, 0);
|
|
assert_eq!(regs.driver_feature_select, 0);
|
|
assert_eq!(regs.queue_select, 0);
|
|
assert_eq!(
|
|
regs.msix_config.load(Ordering::Acquire),
|
|
VIRTQ_MSI_NO_VECTOR
|
|
);
|
|
assert!(
|
|
regs.msix_queues
|
|
.lock()
|
|
.unwrap()
|
|
.iter()
|
|
.all(|v| *v == VIRTQ_MSI_NO_VECTOR)
|
|
);
|
|
}
|
|
|
|
fn make_regs(config_generation: u8) -> VirtioPciCommonConfig {
|
|
let dev: Arc<Mutex<dyn VirtioDevice>> = Arc::new(Mutex::new(DummyDevice(0)));
|
|
VirtioPciCommonConfig {
|
|
device: dev,
|
|
driver_status: Arc::new(AtomicU8::new(0)),
|
|
config_generation: Arc::new(AtomicU8::new(config_generation)),
|
|
config_changed: Arc::new(AtomicBool::new(false)),
|
|
device_feature_select: 0,
|
|
driver_feature_select: 0,
|
|
queue_select: 0,
|
|
msix_config: Arc::new(AtomicU16::new(0)),
|
|
msix_queues: Arc::new(Mutex::new(vec![0; 1])),
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
fn consume_config_change_bumps_when_flag_set() {
|
|
let regs = make_regs(0x10);
|
|
regs.config_changed.store(true, Ordering::Release);
|
|
regs.consume_config_change();
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0x11);
|
|
assert!(!regs.config_changed.load(Ordering::Acquire));
|
|
}
|
|
|
|
#[test]
|
|
fn consume_config_change_is_noop_when_flag_clear() {
|
|
let regs = make_regs(0x10);
|
|
regs.consume_config_change();
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0x10);
|
|
assert!(!regs.config_changed.load(Ordering::Acquire));
|
|
}
|
|
|
|
#[test]
|
|
fn consume_config_change_coalesces_multiple_sets() {
|
|
let regs = make_regs(0x10);
|
|
regs.config_changed.store(true, Ordering::Release);
|
|
regs.config_changed.store(true, Ordering::Release);
|
|
regs.config_changed.store(true, Ordering::Release);
|
|
regs.consume_config_change();
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0x11);
|
|
regs.consume_config_change();
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0x11);
|
|
}
|
|
|
|
#[test]
|
|
fn consume_config_change_wraps_at_u8_max() {
|
|
let regs = make_regs(0xff);
|
|
regs.config_changed.store(true, Ordering::Release);
|
|
regs.consume_config_change();
|
|
assert_eq!(regs.config_generation.load(Ordering::Acquire), 0x00);
|
|
}
|
|
}
|