mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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7dd260f82f
This struct contains all configuration fields that controls the way how we generate CPUID for the guest on x86_64. This allows cleaner extension when adding new configuration fields. Signed-off-by: Bo Chen <chen.bo@intel.com>
1467 lines
49 KiB
Rust
1467 lines
49 KiB
Rust
// Copyright © 2020, Oracle and/or its affiliates.
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//
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// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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use std::sync::Arc;
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pub mod interrupts;
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pub mod layout;
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mod mpspec;
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mod mptable;
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pub mod regs;
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use crate::GuestMemoryMmap;
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use crate::InitramfsConfig;
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use crate::RegionType;
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use hypervisor::arch::x86::{CpuIdEntry, CPUID_FLAG_VALID_INDEX};
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use hypervisor::{CpuVendor, HypervisorCpuError, HypervisorError};
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use linux_loader::loader::bootparam::boot_params;
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use linux_loader::loader::elf::start_info::{
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hvm_memmap_table_entry, hvm_modlist_entry, hvm_start_info,
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};
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use std::collections::BTreeMap;
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use std::mem;
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use vm_memory::{
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Address, ByteValued, Bytes, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic,
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GuestMemoryRegion, GuestUsize,
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};
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mod smbios;
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use std::arch::x86_64;
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#[cfg(feature = "tdx")]
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pub mod tdx;
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// CPUID feature bits
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const TSC_DEADLINE_TIMER_ECX_BIT: u8 = 24; // tsc deadline timer ecx bit.
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const HYPERVISOR_ECX_BIT: u8 = 31; // Hypervisor ecx bit.
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const MTRR_EDX_BIT: u8 = 12; // Hypervisor ecx bit.
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const INVARIANT_TSC_EDX_BIT: u8 = 8; // Invariant TSC bit on 0x8000_0007 EDX
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// KVM feature bits
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_CLOCKSOURCE_BIT: u8 = 0;
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_CLOCKSOURCE2_BIT: u8 = 3;
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_CLOCKSOURCE_STABLE_BIT: u8 = 24;
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_ASYNC_PF_BIT: u8 = 4;
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_ASYNC_PF_VMEXIT_BIT: u8 = 10;
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_STEAL_TIME_BIT: u8 = 5;
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pub const _NSIG: i32 = 65;
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#[derive(Debug, Copy, Clone)]
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/// Specifies the entry point address where the guest must start
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/// executing code, as well as which of the supported boot protocols
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/// is to be used to configure the guest initial state.
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pub struct EntryPoint {
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/// Address in guest memory where the guest must start execution
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pub entry_addr: GuestAddress,
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}
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const E820_RAM: u32 = 1;
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const E820_RESERVED: u32 = 2;
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#[derive(Clone)]
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pub struct SgxEpcSection {
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start: GuestAddress,
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size: GuestUsize,
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}
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impl SgxEpcSection {
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pub fn new(start: GuestAddress, size: GuestUsize) -> Self {
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SgxEpcSection { start, size }
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}
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pub fn start(&self) -> GuestAddress {
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self.start
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}
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pub fn size(&self) -> GuestUsize {
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self.size
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}
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}
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#[derive(Clone)]
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pub struct SgxEpcRegion {
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start: GuestAddress,
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size: GuestUsize,
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epc_sections: BTreeMap<String, SgxEpcSection>,
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}
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impl SgxEpcRegion {
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pub fn new(start: GuestAddress, size: GuestUsize) -> Self {
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SgxEpcRegion {
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start,
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size,
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epc_sections: BTreeMap::new(),
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}
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}
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pub fn start(&self) -> GuestAddress {
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self.start
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}
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pub fn size(&self) -> GuestUsize {
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self.size
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}
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pub fn epc_sections(&self) -> &BTreeMap<String, SgxEpcSection> {
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&self.epc_sections
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}
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pub fn insert(&mut self, id: String, epc_section: SgxEpcSection) {
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self.epc_sections.insert(id, epc_section);
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}
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}
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// This is a workaround to the Rust enforcement specifying that any implementation of a foreign
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// trait (in this case `DataInit`) where:
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// * the type that is implementing the trait is foreign or
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// * all of the parameters being passed to the trait (if there are any) are also foreign
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// is prohibited.
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#[derive(Copy, Clone, Default)]
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struct StartInfoWrapper(hvm_start_info);
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#[derive(Copy, Clone, Default)]
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struct MemmapTableEntryWrapper(hvm_memmap_table_entry);
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#[derive(Copy, Clone, Default)]
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struct ModlistEntryWrapper(hvm_modlist_entry);
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// SAFETY: data structure only contain a series of integers
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unsafe impl ByteValued for StartInfoWrapper {}
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// SAFETY: data structure only contain a series of integers
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unsafe impl ByteValued for MemmapTableEntryWrapper {}
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// SAFETY: data structure only contain a series of integers
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unsafe impl ByteValued for ModlistEntryWrapper {}
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// This is a workaround to the Rust enforcement specifying that any implementation of a foreign
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// trait (in this case `DataInit`) where:
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// * the type that is implementing the trait is foreign or
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// * all of the parameters being passed to the trait (if there are any) are also foreign
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// is prohibited.
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#[derive(Copy, Clone, Default)]
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struct BootParamsWrapper(boot_params);
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// SAFETY: BootParamsWrap is a wrapper over `boot_params` (a series of ints).
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unsafe impl ByteValued for BootParamsWrapper {}
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pub struct CpuidConfig {
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pub sgx_epc_sections: Option<Vec<SgxEpcSection>>,
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pub phys_bits: u8,
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pub kvm_hyperv: bool,
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#[cfg(feature = "tdx")]
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pub tdx: bool,
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}
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#[derive(Debug)]
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pub enum Error {
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/// Error writing MP table to memory.
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MpTableSetup(mptable::Error),
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/// Error configuring the general purpose registers
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RegsConfiguration(regs::Error),
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/// Error configuring the special registers
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SregsConfiguration(regs::Error),
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/// Error configuring the floating point related registers
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FpuConfiguration(regs::Error),
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/// Error configuring the MSR registers
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MsrsConfiguration(regs::Error),
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/// Failed to set supported CPUs.
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SetSupportedCpusFailed(anyhow::Error),
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/// Cannot set the local interruption due to bad configuration.
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LocalIntConfiguration(anyhow::Error),
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/// Error setting up SMBIOS table
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SmbiosSetup(smbios::Error),
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/// Could not find any SGX EPC section
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NoSgxEpcSection,
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/// Missing SGX CPU feature
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MissingSgxFeature,
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/// Missing SGX_LC CPU feature
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MissingSgxLaunchControlFeature,
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/// Error getting supported CPUID through the hypervisor (kvm/mshv) API
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CpuidGetSupported(HypervisorError),
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/// Error populating CPUID with KVM HyperV emulation details
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CpuidKvmHyperV(vmm_sys_util::fam::Error),
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/// Error populating CPUID with CPU identification
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CpuidIdentification(vmm_sys_util::fam::Error),
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/// Error checking CPUID compatibility
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CpuidCheckCompatibility,
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// Error writing EBDA address
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EbdaSetup(vm_memory::GuestMemoryError),
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// Error getting CPU TSC frequency
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GetTscFrequency(HypervisorCpuError),
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/// Error retrieving TDX capabilities through the hypervisor (kvm/mshv) API
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#[cfg(feature = "tdx")]
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TdxCapabilities(HypervisorError),
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}
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impl From<Error> for super::Error {
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fn from(e: Error) -> super::Error {
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super::Error::PlatformSpecific(e)
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}
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}
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#[derive(Copy, Clone, Debug)]
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pub enum CpuidReg {
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EAX,
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EBX,
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ECX,
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EDX,
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}
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pub struct CpuidPatch {
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pub function: u32,
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pub index: u32,
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pub flags_bit: Option<u8>,
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pub eax_bit: Option<u8>,
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pub ebx_bit: Option<u8>,
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pub ecx_bit: Option<u8>,
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pub edx_bit: Option<u8>,
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}
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impl CpuidPatch {
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pub fn set_cpuid_reg(
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cpuid: &mut Vec<CpuIdEntry>,
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function: u32,
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index: Option<u32>,
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reg: CpuidReg,
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value: u32,
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) {
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let mut entry_found = false;
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for entry in cpuid.iter_mut() {
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if entry.function == function && (index.is_none() || index.unwrap() == entry.index) {
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entry_found = true;
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match reg {
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CpuidReg::EAX => {
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entry.eax = value;
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}
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CpuidReg::EBX => {
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entry.ebx = value;
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}
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CpuidReg::ECX => {
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entry.ecx = value;
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}
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CpuidReg::EDX => {
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entry.edx = value;
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}
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}
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}
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}
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if entry_found {
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return;
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}
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// Entry not found, so let's add it.
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if let Some(index) = index {
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let mut entry = CpuIdEntry {
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function,
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index,
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flags: CPUID_FLAG_VALID_INDEX,
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..Default::default()
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};
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match reg {
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CpuidReg::EAX => {
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entry.eax = value;
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}
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CpuidReg::EBX => {
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entry.ebx = value;
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}
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CpuidReg::ECX => {
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entry.ecx = value;
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}
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CpuidReg::EDX => {
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entry.edx = value;
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}
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}
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cpuid.push(entry);
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}
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}
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pub fn patch_cpuid(cpuid: &mut [CpuIdEntry], patches: Vec<CpuidPatch>) {
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for entry in cpuid {
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for patch in patches.iter() {
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if entry.function == patch.function && entry.index == patch.index {
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if let Some(flags_bit) = patch.flags_bit {
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entry.flags |= 1 << flags_bit;
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}
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if let Some(eax_bit) = patch.eax_bit {
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entry.eax |= 1 << eax_bit;
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}
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if let Some(ebx_bit) = patch.ebx_bit {
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entry.ebx |= 1 << ebx_bit;
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}
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if let Some(ecx_bit) = patch.ecx_bit {
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entry.ecx |= 1 << ecx_bit;
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}
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if let Some(edx_bit) = patch.edx_bit {
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entry.edx |= 1 << edx_bit;
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}
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}
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}
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}
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}
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pub fn is_feature_enabled(
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cpuid: &[CpuIdEntry],
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function: u32,
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index: u32,
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reg: CpuidReg,
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feature_bit: usize,
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) -> bool {
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let mask = 1 << feature_bit;
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for entry in cpuid {
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if entry.function == function && entry.index == index {
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let reg_val = match reg {
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CpuidReg::EAX => entry.eax,
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CpuidReg::EBX => entry.ebx,
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CpuidReg::ECX => entry.ecx,
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CpuidReg::EDX => entry.edx,
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};
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return (reg_val & mask) == mask;
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}
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}
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false
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}
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}
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#[derive(Debug)]
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enum CpuidCompatibleCheck {
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BitwiseSubset, // bitwise subset
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Equal, // equal in value
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NumNotGreater, // smaller or equal as a number
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}
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pub struct CpuidFeatureEntry {
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function: u32,
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index: u32,
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feature_reg: CpuidReg,
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compatible_check: CpuidCompatibleCheck,
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}
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impl CpuidFeatureEntry {
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fn checked_feature_entry_list() -> Vec<CpuidFeatureEntry> {
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vec![
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// The following list includes all hardware features bits from
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// the CPUID Wiki Page: https://en.wikipedia.org/wiki/CPUID
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// Leaf 0x1, ECX/EDX, feature bits
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CpuidFeatureEntry {
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function: 1,
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index: 0,
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feature_reg: CpuidReg::ECX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 1,
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index: 0,
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feature_reg: CpuidReg::EDX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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// Leaf 0x7, EAX/EBX/ECX/EDX, extended features
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CpuidFeatureEntry {
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function: 7,
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index: 0,
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feature_reg: CpuidReg::EAX,
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compatible_check: CpuidCompatibleCheck::NumNotGreater,
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},
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CpuidFeatureEntry {
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function: 7,
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index: 0,
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feature_reg: CpuidReg::EBX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 7,
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index: 0,
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feature_reg: CpuidReg::ECX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 7,
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index: 0,
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feature_reg: CpuidReg::EDX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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// Leaf 0x7 subleaf 0x1, EAX, extended features
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CpuidFeatureEntry {
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function: 7,
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index: 1,
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feature_reg: CpuidReg::EAX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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// Leaf 0x8000_0001, ECX/EDX, CPUID features bits
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CpuidFeatureEntry {
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function: 0x8000_0001,
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index: 0,
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feature_reg: CpuidReg::ECX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 0x8000_0001,
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index: 0,
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feature_reg: CpuidReg::EDX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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// KVM CPUID bits: https://www.kernel.org/doc/html/latest/virt/kvm/cpuid.html
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// Leaf 0x4000_0000, EAX/EBX/ECX/EDX, KVM CPUID SIGNATURE
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CpuidFeatureEntry {
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function: 0x4000_0000,
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index: 0,
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feature_reg: CpuidReg::EAX,
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compatible_check: CpuidCompatibleCheck::NumNotGreater,
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},
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CpuidFeatureEntry {
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function: 0x4000_0000,
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index: 0,
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feature_reg: CpuidReg::EBX,
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compatible_check: CpuidCompatibleCheck::Equal,
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},
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CpuidFeatureEntry {
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function: 0x4000_0000,
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index: 0,
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feature_reg: CpuidReg::ECX,
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compatible_check: CpuidCompatibleCheck::Equal,
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},
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CpuidFeatureEntry {
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function: 0x4000_0000,
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index: 0,
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feature_reg: CpuidReg::EDX,
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compatible_check: CpuidCompatibleCheck::Equal,
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},
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// Leaf 0x4000_0001, EAX/EBX/ECX/EDX, KVM CPUID features
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CpuidFeatureEntry {
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function: 0x4000_0001,
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index: 0,
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feature_reg: CpuidReg::EAX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 0x4000_0001,
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index: 0,
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feature_reg: CpuidReg::EBX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 0x4000_0001,
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index: 0,
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feature_reg: CpuidReg::ECX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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CpuidFeatureEntry {
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function: 0x4000_0001,
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index: 0,
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feature_reg: CpuidReg::EDX,
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compatible_check: CpuidCompatibleCheck::BitwiseSubset,
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},
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]
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}
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fn get_features_from_cpuid(
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cpuid: &[CpuIdEntry],
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feature_entry_list: &[CpuidFeatureEntry],
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) -> Vec<u32> {
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let mut features = vec![0; feature_entry_list.len()];
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for (i, feature_entry) in feature_entry_list.iter().enumerate() {
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for cpuid_entry in cpuid {
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if cpuid_entry.function == feature_entry.function
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&& cpuid_entry.index == feature_entry.index
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{
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match feature_entry.feature_reg {
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CpuidReg::EAX => {
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features[i] = cpuid_entry.eax;
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}
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CpuidReg::EBX => {
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features[i] = cpuid_entry.ebx;
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}
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CpuidReg::ECX => {
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features[i] = cpuid_entry.ecx;
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}
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CpuidReg::EDX => {
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features[i] = cpuid_entry.edx;
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}
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}
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break;
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}
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}
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}
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features
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}
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// The function returns `Error` (a.k.a. "incompatible"), when the CPUID features from `src_vm_cpuid`
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// is not a subset of those of the `dest_vm_cpuid`.
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pub fn check_cpuid_compatibility(
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src_vm_cpuid: &[CpuIdEntry],
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dest_vm_cpuid: &[CpuIdEntry],
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) -> Result<(), Error> {
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let feature_entry_list = &Self::checked_feature_entry_list();
|
|
let src_vm_features = Self::get_features_from_cpuid(src_vm_cpuid, feature_entry_list);
|
|
let dest_vm_features = Self::get_features_from_cpuid(dest_vm_cpuid, feature_entry_list);
|
|
|
|
// Loop on feature bit and check if the 'source vm' feature is a subset
|
|
// of those of the 'destination vm' feature
|
|
let mut compatible = true;
|
|
for (i, (src_vm_feature, dest_vm_feature)) in src_vm_features
|
|
.iter()
|
|
.zip(dest_vm_features.iter())
|
|
.enumerate()
|
|
{
|
|
let entry = &feature_entry_list[i];
|
|
let entry_compatible = match entry.compatible_check {
|
|
CpuidCompatibleCheck::BitwiseSubset => {
|
|
let different_feature_bits = src_vm_feature ^ dest_vm_feature;
|
|
let src_vm_feature_bits_only = different_feature_bits & src_vm_feature;
|
|
src_vm_feature_bits_only == 0
|
|
}
|
|
CpuidCompatibleCheck::Equal => src_vm_feature == dest_vm_feature,
|
|
CpuidCompatibleCheck::NumNotGreater => src_vm_feature <= dest_vm_feature,
|
|
};
|
|
if !entry_compatible {
|
|
error!(
|
|
"Detected incompatible CPUID entry: leaf={:#02x} (subleaf={:#02x}), register='{:?}', \
|
|
compatilbe_check='{:?}', source VM feature='{:#04x}', destination VM feature'{:#04x}'.",
|
|
entry.function, entry.index, entry.feature_reg,
|
|
entry.compatible_check, src_vm_feature, dest_vm_feature
|
|
);
|
|
|
|
compatible = false;
|
|
}
|
|
}
|
|
|
|
if compatible {
|
|
info!("No CPU incompatibility detected.");
|
|
Ok(())
|
|
} else {
|
|
Err(Error::CpuidCheckCompatibility)
|
|
}
|
|
}
|
|
}
|
|
|
|
pub fn generate_common_cpuid(
|
|
hypervisor: &Arc<dyn hypervisor::Hypervisor>,
|
|
config: &CpuidConfig,
|
|
) -> super::Result<Vec<CpuIdEntry>> {
|
|
// SAFETY: cpuid called with valid leaves
|
|
if unsafe { x86_64::__cpuid(1) }.ecx & 1 << HYPERVISOR_ECX_BIT == 1 << HYPERVISOR_ECX_BIT {
|
|
// SAFETY: cpuid called with valid leaves
|
|
let hypervisor_cpuid = unsafe { x86_64::__cpuid(0x4000_0000) };
|
|
|
|
let mut identifier: [u8; 12] = [0; 12];
|
|
identifier[0..4].copy_from_slice(&hypervisor_cpuid.ebx.to_le_bytes()[..]);
|
|
identifier[4..8].copy_from_slice(&hypervisor_cpuid.ecx.to_le_bytes()[..]);
|
|
identifier[8..12].copy_from_slice(&hypervisor_cpuid.edx.to_le_bytes()[..]);
|
|
|
|
info!(
|
|
"Running under nested virtualisation. Hypervisor string: {}",
|
|
String::from_utf8_lossy(&identifier)
|
|
);
|
|
}
|
|
|
|
info!(
|
|
"Generating guest CPUID for with physical address size: {}",
|
|
config.phys_bits
|
|
);
|
|
let cpuid_patches = vec![
|
|
// Patch tsc deadline timer bit
|
|
CpuidPatch {
|
|
function: 1,
|
|
index: 0,
|
|
flags_bit: None,
|
|
eax_bit: None,
|
|
ebx_bit: None,
|
|
ecx_bit: Some(TSC_DEADLINE_TIMER_ECX_BIT),
|
|
edx_bit: None,
|
|
},
|
|
// Patch hypervisor bit
|
|
CpuidPatch {
|
|
function: 1,
|
|
index: 0,
|
|
flags_bit: None,
|
|
eax_bit: None,
|
|
ebx_bit: None,
|
|
ecx_bit: Some(HYPERVISOR_ECX_BIT),
|
|
edx_bit: None,
|
|
},
|
|
// Enable MTRR feature
|
|
CpuidPatch {
|
|
function: 1,
|
|
index: 0,
|
|
flags_bit: None,
|
|
eax_bit: None,
|
|
ebx_bit: None,
|
|
ecx_bit: None,
|
|
edx_bit: Some(MTRR_EDX_BIT),
|
|
},
|
|
];
|
|
|
|
// Supported CPUID
|
|
let mut cpuid = hypervisor
|
|
.get_supported_cpuid()
|
|
.map_err(Error::CpuidGetSupported)?;
|
|
|
|
CpuidPatch::patch_cpuid(&mut cpuid, cpuid_patches);
|
|
|
|
if let Some(sgx_epc_sections) = &config.sgx_epc_sections {
|
|
update_cpuid_sgx(&mut cpuid, sgx_epc_sections)?;
|
|
}
|
|
|
|
#[cfg(feature = "tdx")]
|
|
let tdx_capabilities = if config.tdx {
|
|
let caps = hypervisor
|
|
.tdx_capabilities()
|
|
.map_err(Error::TdxCapabilities)?;
|
|
info!("TDX capabilities {:#?}", caps);
|
|
Some(caps)
|
|
} else {
|
|
None
|
|
};
|
|
|
|
// Update some existing CPUID
|
|
for entry in cpuid.as_mut_slice().iter_mut() {
|
|
match entry.function {
|
|
0xd =>
|
|
{
|
|
#[cfg(feature = "tdx")]
|
|
if let Some(caps) = &tdx_capabilities {
|
|
let xcr0_mask: u64 = 0x82ff;
|
|
let xss_mask: u64 = !xcr0_mask;
|
|
if entry.index == 0 {
|
|
entry.eax &= (caps.xfam_fixed0 as u32) & (xcr0_mask as u32);
|
|
entry.eax |= (caps.xfam_fixed1 as u32) & (xcr0_mask as u32);
|
|
entry.edx &= ((caps.xfam_fixed0 & xcr0_mask) >> 32) as u32;
|
|
entry.edx |= ((caps.xfam_fixed1 & xcr0_mask) >> 32) as u32;
|
|
} else if entry.index == 1 {
|
|
entry.ecx &= (caps.xfam_fixed0 as u32) & (xss_mask as u32);
|
|
entry.ecx |= (caps.xfam_fixed1 as u32) & (xss_mask as u32);
|
|
entry.edx &= ((caps.xfam_fixed0 & xss_mask) >> 32) as u32;
|
|
entry.edx |= ((caps.xfam_fixed1 & xss_mask) >> 32) as u32;
|
|
}
|
|
}
|
|
}
|
|
// Copy host L2 cache details if not populated by KVM
|
|
0x8000_0006 => {
|
|
if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 {
|
|
// SAFETY: cpuid called with valid leaves
|
|
if unsafe { std::arch::x86_64::__cpuid(0x8000_0000).eax } >= 0x8000_0006 {
|
|
// SAFETY: cpuid called with valid leaves
|
|
let leaf = unsafe { std::arch::x86_64::__cpuid(0x8000_0006) };
|
|
entry.eax = leaf.eax;
|
|
entry.ebx = leaf.ebx;
|
|
entry.ecx = leaf.ecx;
|
|
entry.edx = leaf.edx;
|
|
}
|
|
}
|
|
}
|
|
// Set CPU physical bits
|
|
0x8000_0008 => {
|
|
entry.eax = (entry.eax & 0xffff_ff00) | (config.phys_bits as u32 & 0xff);
|
|
}
|
|
0x4000_0001 => {
|
|
// These features are not supported by TDX
|
|
#[cfg(feature = "tdx")]
|
|
if config.tdx {
|
|
entry.eax &= !(1 << KVM_FEATURE_CLOCKSOURCE_BIT
|
|
| 1 << KVM_FEATURE_CLOCKSOURCE2_BIT
|
|
| 1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
|
|
| 1 << KVM_FEATURE_ASYNC_PF_BIT
|
|
| 1 << KVM_FEATURE_ASYNC_PF_VMEXIT_BIT
|
|
| 1 << KVM_FEATURE_STEAL_TIME_BIT)
|
|
}
|
|
}
|
|
_ => {}
|
|
}
|
|
}
|
|
|
|
// Copy CPU identification string
|
|
for i in 0x8000_0002..=0x8000_0004 {
|
|
cpuid.retain(|c| c.function != i);
|
|
// SAFETY: call cpuid with valid leaves
|
|
let leaf = unsafe { std::arch::x86_64::__cpuid(i) };
|
|
cpuid.push(CpuIdEntry {
|
|
function: i,
|
|
eax: leaf.eax,
|
|
ebx: leaf.ebx,
|
|
ecx: leaf.ecx,
|
|
edx: leaf.edx,
|
|
..Default::default()
|
|
});
|
|
}
|
|
|
|
if config.kvm_hyperv {
|
|
// Remove conflicting entries
|
|
cpuid.retain(|c| c.function != 0x4000_0000);
|
|
cpuid.retain(|c| c.function != 0x4000_0001);
|
|
// See "Hypervisor Top Level Functional Specification" for details
|
|
// Compliance with "Hv#1" requires leaves up to 0x4000_000a
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x40000000,
|
|
eax: 0x4000000a, // Maximum cpuid leaf
|
|
ebx: 0x756e694c, // "Linu"
|
|
ecx: 0x564b2078, // "x KV"
|
|
edx: 0x7648204d, // "M Hv"
|
|
..Default::default()
|
|
});
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x40000001,
|
|
eax: 0x31237648, // "Hv#1"
|
|
..Default::default()
|
|
});
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x40000002,
|
|
eax: 0x3839, // "Build number"
|
|
ebx: 0xa0000, // "Version"
|
|
..Default::default()
|
|
});
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x4000_0003,
|
|
eax: 1 << 1 // AccessPartitionReferenceCounter
|
|
| 1 << 2 // AccessSynicRegs
|
|
| 1 << 3 // AccessSyntheticTimerRegs
|
|
| 1 << 9, // AccessPartitionReferenceTsc
|
|
edx: 1 << 3, // CPU dynamic partitioning
|
|
..Default::default()
|
|
});
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x4000_0004,
|
|
eax: 1 << 5, // Recommend relaxed timing
|
|
..Default::default()
|
|
});
|
|
for i in 0x4000_0005..=0x4000_000a {
|
|
cpuid.push(CpuIdEntry {
|
|
function: i,
|
|
..Default::default()
|
|
});
|
|
}
|
|
}
|
|
|
|
Ok(cpuid)
|
|
}
|
|
|
|
pub fn configure_vcpu(
|
|
vcpu: &Arc<dyn hypervisor::Vcpu>,
|
|
id: u8,
|
|
boot_setup: Option<(EntryPoint, &GuestMemoryAtomic<GuestMemoryMmap>)>,
|
|
cpuid: Vec<CpuIdEntry>,
|
|
kvm_hyperv: bool,
|
|
cpu_vendor: CpuVendor,
|
|
topology: Option<(u8, u8, u8)>,
|
|
) -> super::Result<()> {
|
|
// Per vCPU CPUID changes; common are handled via generate_common_cpuid()
|
|
let mut cpuid = cpuid;
|
|
CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
|
|
CpuidPatch::set_cpuid_reg(&mut cpuid, 0x1f, None, CpuidReg::EDX, u32::from(id));
|
|
if matches!(cpu_vendor, CpuVendor::AMD) {
|
|
CpuidPatch::set_cpuid_reg(
|
|
&mut cpuid,
|
|
0x8000_001e,
|
|
Some(0),
|
|
CpuidReg::EAX,
|
|
u32::from(id),
|
|
);
|
|
}
|
|
|
|
if let Some(t) = topology {
|
|
update_cpuid_topology(&mut cpuid, t.0, t.1, t.2, cpu_vendor, id);
|
|
}
|
|
|
|
// Set ApicId in cpuid for each vcpu
|
|
// SAFETY: get host cpuid when eax=1
|
|
let mut cpu_ebx = unsafe { core::arch::x86_64::__cpuid(1) }.ebx;
|
|
cpu_ebx &= 0xffffff;
|
|
cpu_ebx |= (id as u32) << 24;
|
|
CpuidPatch::set_cpuid_reg(&mut cpuid, 0x1, None, CpuidReg::EBX, cpu_ebx);
|
|
|
|
// The TSC frequency CPUID leaf should not be included when running with HyperV emulation
|
|
if !kvm_hyperv {
|
|
if let Some(tsc_khz) = vcpu.tsc_khz().map_err(Error::GetTscFrequency)? {
|
|
// Need to check that the TSC doesn't vary with dynamic frequency
|
|
// SAFETY: cpuid called with valid leaves
|
|
if unsafe { std::arch::x86_64::__cpuid(0x8000_0007) }.edx
|
|
& (1u32 << INVARIANT_TSC_EDX_BIT)
|
|
> 0
|
|
{
|
|
CpuidPatch::set_cpuid_reg(
|
|
&mut cpuid,
|
|
0x4000_0000,
|
|
None,
|
|
CpuidReg::EAX,
|
|
0x4000_0010,
|
|
);
|
|
cpuid.retain(|c| c.function != 0x4000_0010);
|
|
cpuid.push(CpuIdEntry {
|
|
function: 0x4000_0010,
|
|
eax: tsc_khz,
|
|
ebx: 1000000, /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
|
|
* APIC_BUS_CYCLE_NS */
|
|
..Default::default()
|
|
});
|
|
};
|
|
}
|
|
}
|
|
|
|
vcpu.set_cpuid2(&cpuid)
|
|
.map_err(|e| Error::SetSupportedCpusFailed(e.into()))?;
|
|
|
|
if kvm_hyperv {
|
|
vcpu.enable_hyperv_synic().unwrap();
|
|
}
|
|
|
|
regs::setup_msrs(vcpu).map_err(Error::MsrsConfiguration)?;
|
|
if let Some((kernel_entry_point, guest_memory)) = boot_setup {
|
|
regs::setup_regs(vcpu, kernel_entry_point.entry_addr.raw_value())
|
|
.map_err(Error::RegsConfiguration)?;
|
|
regs::setup_fpu(vcpu).map_err(Error::FpuConfiguration)?;
|
|
regs::setup_sregs(&guest_memory.memory(), vcpu).map_err(Error::SregsConfiguration)?;
|
|
}
|
|
interrupts::set_lint(vcpu).map_err(|e| Error::LocalIntConfiguration(e.into()))?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Returns a Vec of the valid memory addresses.
|
|
/// These should be used to configure the GuestMemory structure for the platform.
|
|
/// For x86_64 all addresses are valid from the start of the kernel except a
|
|
/// carve out at the end of 32bit address space.
|
|
pub fn arch_memory_regions() -> Vec<(GuestAddress, usize, RegionType)> {
|
|
vec![
|
|
// 0 GiB ~ 3GiB: memory before the gap
|
|
(
|
|
GuestAddress(0),
|
|
layout::MEM_32BIT_RESERVED_START.raw_value() as usize,
|
|
RegionType::Ram,
|
|
),
|
|
// 4 GiB ~ inf: memory after the gap
|
|
(layout::RAM_64BIT_START, usize::MAX, RegionType::Ram),
|
|
// 3 GiB ~ 3712 MiB: 32-bit device memory hole
|
|
(
|
|
layout::MEM_32BIT_RESERVED_START,
|
|
layout::MEM_32BIT_DEVICES_SIZE as usize,
|
|
RegionType::SubRegion,
|
|
),
|
|
// 3712 MiB ~ 3968 MiB: 32-bit reserved memory hole
|
|
(
|
|
layout::MEM_32BIT_RESERVED_START.unchecked_add(layout::MEM_32BIT_DEVICES_SIZE),
|
|
(layout::MEM_32BIT_RESERVED_SIZE - layout::MEM_32BIT_DEVICES_SIZE) as usize,
|
|
RegionType::Reserved,
|
|
),
|
|
]
|
|
}
|
|
|
|
/// Configures the system and should be called once per vm before starting vcpu threads.
|
|
///
|
|
/// # Arguments
|
|
///
|
|
/// * `guest_mem` - The memory to be used by the guest.
|
|
/// * `cmdline_addr` - Address in `guest_mem` where the kernel command line was loaded.
|
|
/// * `cmdline_size` - Size of the kernel command line in bytes including the null terminator.
|
|
/// * `num_cpus` - Number of virtual CPUs the guest will have.
|
|
#[allow(clippy::too_many_arguments)]
|
|
pub fn configure_system(
|
|
guest_mem: &GuestMemoryMmap,
|
|
cmdline_addr: GuestAddress,
|
|
initramfs: &Option<InitramfsConfig>,
|
|
_num_cpus: u8,
|
|
rsdp_addr: Option<GuestAddress>,
|
|
sgx_epc_region: Option<SgxEpcRegion>,
|
|
serial_number: Option<&str>,
|
|
uuid: Option<&str>,
|
|
oem_strings: Option<&[&str]>,
|
|
) -> super::Result<()> {
|
|
// Write EBDA address to location where ACPICA expects to find it
|
|
guest_mem
|
|
.write_obj((layout::EBDA_START.0 >> 4) as u16, layout::EBDA_POINTER)
|
|
.map_err(Error::EbdaSetup)?;
|
|
|
|
let size = smbios::setup_smbios(guest_mem, serial_number, uuid, oem_strings)
|
|
.map_err(Error::SmbiosSetup)?;
|
|
|
|
// Place the MP table after the SMIOS table aligned to 16 bytes
|
|
let offset = GuestAddress(layout::SMBIOS_START).unchecked_add(size);
|
|
let offset = GuestAddress((offset.0 + 16) & !0xf);
|
|
mptable::setup_mptable(offset, guest_mem, _num_cpus).map_err(Error::MpTableSetup)?;
|
|
|
|
// Check that the RAM is not smaller than the RSDP start address
|
|
if let Some(rsdp_addr) = rsdp_addr {
|
|
if rsdp_addr.0 > guest_mem.last_addr().0 {
|
|
return Err(super::Error::RsdpPastRamEnd);
|
|
}
|
|
}
|
|
|
|
configure_pvh(
|
|
guest_mem,
|
|
cmdline_addr,
|
|
initramfs,
|
|
rsdp_addr,
|
|
sgx_epc_region,
|
|
)
|
|
}
|
|
|
|
fn configure_pvh(
|
|
guest_mem: &GuestMemoryMmap,
|
|
cmdline_addr: GuestAddress,
|
|
initramfs: &Option<InitramfsConfig>,
|
|
rsdp_addr: Option<GuestAddress>,
|
|
sgx_epc_region: Option<SgxEpcRegion>,
|
|
) -> super::Result<()> {
|
|
const XEN_HVM_START_MAGIC_VALUE: u32 = 0x336ec578;
|
|
|
|
let mut start_info: StartInfoWrapper = StartInfoWrapper(hvm_start_info::default());
|
|
|
|
start_info.0.magic = XEN_HVM_START_MAGIC_VALUE;
|
|
start_info.0.version = 1; // pvh has version 1
|
|
start_info.0.nr_modules = 0;
|
|
start_info.0.cmdline_paddr = cmdline_addr.raw_value();
|
|
start_info.0.memmap_paddr = layout::MEMMAP_START.raw_value();
|
|
|
|
if let Some(rsdp_addr) = rsdp_addr {
|
|
start_info.0.rsdp_paddr = rsdp_addr.0;
|
|
}
|
|
|
|
if let Some(initramfs_config) = initramfs {
|
|
// The initramfs has been written to guest memory already, here we just need to
|
|
// create the module structure that describes it.
|
|
let ramdisk_mod: ModlistEntryWrapper = ModlistEntryWrapper(hvm_modlist_entry {
|
|
paddr: initramfs_config.address.raw_value(),
|
|
size: initramfs_config.size as u64,
|
|
..Default::default()
|
|
});
|
|
|
|
start_info.0.nr_modules += 1;
|
|
start_info.0.modlist_paddr = layout::MODLIST_START.raw_value();
|
|
|
|
// Write the modlist struct to guest memory.
|
|
guest_mem
|
|
.write_obj(ramdisk_mod, layout::MODLIST_START)
|
|
.map_err(super::Error::ModlistSetup)?;
|
|
}
|
|
|
|
// Vector to hold the memory maps which needs to be written to guest memory
|
|
// at MEMMAP_START after all of the mappings are recorded.
|
|
let mut memmap: Vec<hvm_memmap_table_entry> = Vec::new();
|
|
|
|
// Create the memory map entries.
|
|
add_memmap_entry(&mut memmap, 0, layout::EBDA_START.raw_value(), E820_RAM);
|
|
|
|
// Merge continuous memory regions into one region.
|
|
// Note: memory regions from "GuestMemory" are sorted and non-zero sized.
|
|
let ram_regions = {
|
|
let mut ram_regions = Vec::new();
|
|
let mut current_start = guest_mem
|
|
.iter()
|
|
.next()
|
|
.map(GuestMemoryRegion::start_addr)
|
|
.expect("GuestMemory must have one memory region at least")
|
|
.raw_value();
|
|
let mut current_end = current_start;
|
|
|
|
for (start, size) in guest_mem
|
|
.iter()
|
|
.map(|m| (m.start_addr().raw_value(), m.len()))
|
|
{
|
|
if current_end == start {
|
|
// This zone is continuous with the previous one.
|
|
current_end += size;
|
|
} else {
|
|
ram_regions.push((current_start, current_end));
|
|
|
|
current_start = start;
|
|
current_end = start + size;
|
|
}
|
|
}
|
|
|
|
ram_regions.push((current_start, current_end));
|
|
|
|
ram_regions
|
|
};
|
|
|
|
if ram_regions.len() > 2 {
|
|
error!(
|
|
"There should be up to two non-continuous regions, devidided by the
|
|
gap at the end of 32bit address space (e.g. between 3G and 4G)."
|
|
);
|
|
return Err(super::Error::MemmapTableSetup);
|
|
}
|
|
|
|
// Create the memory map entry for memory region before the gap
|
|
{
|
|
let (first_region_start, first_region_end) =
|
|
ram_regions.first().ok_or(super::Error::MemmapTableSetup)?;
|
|
let high_ram_start = layout::HIGH_RAM_START.raw_value();
|
|
let mem_32bit_reserved_start = layout::MEM_32BIT_RESERVED_START.raw_value();
|
|
|
|
if !((first_region_start <= &high_ram_start)
|
|
&& (first_region_end > &high_ram_start)
|
|
&& (first_region_end <= &mem_32bit_reserved_start))
|
|
{
|
|
error!(
|
|
"Unexpected first memory region layout: (start: 0x{:08x}, end: 0x{:08x}).
|
|
high_ram_start: 0x{:08x}, mem_32bit_reserved_start: 0x{:08x}",
|
|
first_region_start, first_region_end, high_ram_start, mem_32bit_reserved_start
|
|
);
|
|
|
|
return Err(super::Error::MemmapTableSetup);
|
|
}
|
|
|
|
info!(
|
|
"create_memmap_entry, start: 0x{:08x}, end: 0x{:08x}",
|
|
high_ram_start, first_region_end
|
|
);
|
|
|
|
add_memmap_entry(
|
|
&mut memmap,
|
|
high_ram_start,
|
|
first_region_end - high_ram_start,
|
|
E820_RAM,
|
|
);
|
|
}
|
|
|
|
// Create the memory map entry for memory region after the gap if any
|
|
if let Some((second_region_start, second_region_end)) = ram_regions.get(1) {
|
|
let ram_64bit_start = layout::RAM_64BIT_START.raw_value();
|
|
|
|
if second_region_start != &ram_64bit_start {
|
|
error!(
|
|
"Unexpected second memory region layout: start: 0x{:08x}, ram_64bit_start: 0x{:08x}",
|
|
second_region_start, ram_64bit_start
|
|
);
|
|
|
|
return Err(super::Error::MemmapTableSetup);
|
|
}
|
|
|
|
info!(
|
|
"create_memmap_entry, start: 0x{:08x}, end: 0x{:08x}",
|
|
ram_64bit_start, second_region_end
|
|
);
|
|
add_memmap_entry(
|
|
&mut memmap,
|
|
ram_64bit_start,
|
|
second_region_end - ram_64bit_start,
|
|
E820_RAM,
|
|
);
|
|
}
|
|
|
|
add_memmap_entry(
|
|
&mut memmap,
|
|
layout::PCI_MMCONFIG_START.0,
|
|
layout::PCI_MMCONFIG_SIZE,
|
|
E820_RESERVED,
|
|
);
|
|
|
|
if let Some(sgx_epc_region) = sgx_epc_region {
|
|
add_memmap_entry(
|
|
&mut memmap,
|
|
sgx_epc_region.start().raw_value(),
|
|
sgx_epc_region.size(),
|
|
E820_RESERVED,
|
|
);
|
|
}
|
|
|
|
start_info.0.memmap_entries = memmap.len() as u32;
|
|
|
|
// Copy the vector with the memmap table to the MEMMAP_START address
|
|
// which is already saved in the memmap_paddr field of hvm_start_info struct.
|
|
let mut memmap_start_addr = layout::MEMMAP_START;
|
|
|
|
guest_mem
|
|
.checked_offset(
|
|
memmap_start_addr,
|
|
mem::size_of::<hvm_memmap_table_entry>() * start_info.0.memmap_entries as usize,
|
|
)
|
|
.ok_or(super::Error::MemmapTablePastRamEnd)?;
|
|
|
|
// For every entry in the memmap vector, create a MemmapTableEntryWrapper
|
|
// and write it to guest memory.
|
|
for memmap_entry in memmap {
|
|
let map_entry_wrapper: MemmapTableEntryWrapper = MemmapTableEntryWrapper(memmap_entry);
|
|
|
|
guest_mem
|
|
.write_obj(map_entry_wrapper, memmap_start_addr)
|
|
.map_err(|_| super::Error::MemmapTableSetup)?;
|
|
memmap_start_addr =
|
|
memmap_start_addr.unchecked_add(mem::size_of::<hvm_memmap_table_entry>() as u64);
|
|
}
|
|
|
|
// The hvm_start_info struct itself must be stored at PVH_START_INFO
|
|
// address, and %rbx will be initialized to contain PVH_INFO_START prior to
|
|
// starting the guest, as required by the PVH ABI.
|
|
let start_info_addr = layout::PVH_INFO_START;
|
|
|
|
guest_mem
|
|
.checked_offset(start_info_addr, mem::size_of::<hvm_start_info>())
|
|
.ok_or(super::Error::StartInfoPastRamEnd)?;
|
|
|
|
// Write the start_info struct to guest memory.
|
|
guest_mem
|
|
.write_obj(start_info, start_info_addr)
|
|
.map_err(|_| super::Error::StartInfoSetup)?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn add_memmap_entry(memmap: &mut Vec<hvm_memmap_table_entry>, addr: u64, size: u64, mem_type: u32) {
|
|
// Add the table entry to the vector
|
|
memmap.push(hvm_memmap_table_entry {
|
|
addr,
|
|
size,
|
|
type_: mem_type,
|
|
reserved: 0,
|
|
});
|
|
}
|
|
|
|
/// Returns the memory address where the initramfs could be loaded.
|
|
pub fn initramfs_load_addr(
|
|
guest_mem: &GuestMemoryMmap,
|
|
initramfs_size: usize,
|
|
) -> super::Result<u64> {
|
|
let first_region = guest_mem
|
|
.find_region(GuestAddress::new(0))
|
|
.ok_or(super::Error::InitramfsAddress)?;
|
|
// It's safe to cast to usize because the size of a region can't be greater than usize.
|
|
let lowmem_size = first_region.len() as usize;
|
|
|
|
if lowmem_size < initramfs_size {
|
|
return Err(super::Error::InitramfsAddress);
|
|
}
|
|
|
|
let aligned_addr: u64 = ((lowmem_size - initramfs_size) & !(crate::pagesize() - 1)) as u64;
|
|
Ok(aligned_addr)
|
|
}
|
|
|
|
pub fn get_host_cpu_phys_bits(hypervisor: &Arc<dyn hypervisor::Hypervisor>) -> u8 {
|
|
// SAFETY: call cpuid with valid leaves
|
|
unsafe {
|
|
let leaf = x86_64::__cpuid(0x8000_0000);
|
|
|
|
// Detect and handle AMD SME (Secure Memory Encryption) properly.
|
|
// Some physical address bits may become reserved when the feature is enabled.
|
|
// See AMD64 Architecture Programmer's Manual Volume 2, Section 7.10.1
|
|
let reduced = if leaf.eax >= 0x8000_001f
|
|
&& matches!(hypervisor.get_cpu_vendor(), CpuVendor::AMD)
|
|
&& x86_64::__cpuid(0x8000_001f).eax & 0x1 != 0
|
|
{
|
|
(x86_64::__cpuid(0x8000_001f).ebx >> 6) & 0x3f
|
|
} else {
|
|
0
|
|
};
|
|
|
|
if leaf.eax >= 0x8000_0008 {
|
|
let leaf = x86_64::__cpuid(0x8000_0008);
|
|
((leaf.eax & 0xff) - reduced) as u8
|
|
} else {
|
|
36
|
|
}
|
|
}
|
|
}
|
|
|
|
fn update_cpuid_topology(
|
|
cpuid: &mut Vec<CpuIdEntry>,
|
|
threads_per_core: u8,
|
|
cores_per_die: u8,
|
|
dies_per_package: u8,
|
|
cpu_vendor: CpuVendor,
|
|
id: u8,
|
|
) {
|
|
let thread_width = 8 - (threads_per_core - 1).leading_zeros();
|
|
let core_width = (8 - (cores_per_die - 1).leading_zeros()) + thread_width;
|
|
let die_width = (8 - (dies_per_package - 1).leading_zeros()) + core_width;
|
|
|
|
// CPU Topology leaf 0xb
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(0), CpuidReg::EAX, thread_width);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0xb,
|
|
Some(0),
|
|
CpuidReg::EBX,
|
|
u32::from(threads_per_core),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(0), CpuidReg::ECX, 1 << 8);
|
|
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(1), CpuidReg::EAX, die_width);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0xb,
|
|
Some(1),
|
|
CpuidReg::EBX,
|
|
u32::from(dies_per_package * cores_per_die * threads_per_core),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(1), CpuidReg::ECX, 2 << 8);
|
|
|
|
// CPU Topology leaf 0x1f
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(0), CpuidReg::EAX, thread_width);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x1f,
|
|
Some(0),
|
|
CpuidReg::EBX,
|
|
u32::from(threads_per_core),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(0), CpuidReg::ECX, 1 << 8);
|
|
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(1), CpuidReg::EAX, core_width);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x1f,
|
|
Some(1),
|
|
CpuidReg::EBX,
|
|
u32::from(cores_per_die * threads_per_core),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(1), CpuidReg::ECX, 2 << 8);
|
|
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(2), CpuidReg::EAX, die_width);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x1f,
|
|
Some(2),
|
|
CpuidReg::EBX,
|
|
u32::from(dies_per_package * cores_per_die * threads_per_core),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(2), CpuidReg::ECX, 5 << 8);
|
|
|
|
if matches!(cpu_vendor, CpuVendor::AMD) {
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x8000_001e,
|
|
Some(0),
|
|
CpuidReg::EBX,
|
|
((threads_per_core as u32 - 1) << 8) | (id as u32 & 0xff),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x8000_001e,
|
|
Some(0),
|
|
CpuidReg::ECX,
|
|
((dies_per_package as u32 - 1) << 8) | (thread_width + die_width) & 0xff,
|
|
);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x8000_001e, Some(0), CpuidReg::EDX, 0);
|
|
if cores_per_die * threads_per_core > 1 {
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x8000_0001,
|
|
Some(0),
|
|
CpuidReg::ECX,
|
|
(1u32 << 1) | (1u32 << 22),
|
|
);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x0000_0001,
|
|
Some(0),
|
|
CpuidReg::EBX,
|
|
((id as u32) << 24)
|
|
| (8 << 8)
|
|
| (((cores_per_die * threads_per_core) as u32) << 16),
|
|
);
|
|
let cpuid_patches = vec![
|
|
// Patch tsc deadline timer bit
|
|
CpuidPatch {
|
|
function: 1,
|
|
index: 0,
|
|
flags_bit: None,
|
|
eax_bit: None,
|
|
ebx_bit: None,
|
|
ecx_bit: None,
|
|
edx_bit: Some(28),
|
|
},
|
|
];
|
|
CpuidPatch::patch_cpuid(cpuid, cpuid_patches);
|
|
CpuidPatch::set_cpuid_reg(
|
|
cpuid,
|
|
0x8000_0008,
|
|
Some(0),
|
|
CpuidReg::ECX,
|
|
((thread_width + core_width + die_width) << 12)
|
|
| ((cores_per_die * threads_per_core) - 1) as u32,
|
|
);
|
|
} else {
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x8000_0008, Some(0), CpuidReg::ECX, 0u32);
|
|
}
|
|
}
|
|
}
|
|
|
|
// The goal is to update the CPUID sub-leaves to reflect the number of EPC
|
|
// sections exposed to the guest.
|
|
fn update_cpuid_sgx(
|
|
cpuid: &mut Vec<CpuIdEntry>,
|
|
epc_sections: &Vec<SgxEpcSection>,
|
|
) -> Result<(), Error> {
|
|
// Something's wrong if there's no EPC section.
|
|
if epc_sections.is_empty() {
|
|
return Err(Error::NoSgxEpcSection);
|
|
}
|
|
// We can't go further if the hypervisor does not support SGX feature.
|
|
if !CpuidPatch::is_feature_enabled(cpuid, 0x7, 0, CpuidReg::EBX, 2) {
|
|
return Err(Error::MissingSgxFeature);
|
|
}
|
|
// We can't go further if the hypervisor does not support SGX_LC feature.
|
|
if !CpuidPatch::is_feature_enabled(cpuid, 0x7, 0, CpuidReg::ECX, 30) {
|
|
return Err(Error::MissingSgxLaunchControlFeature);
|
|
}
|
|
|
|
// Get host CPUID for leaf 0x12, subleaf 0x2. This is to retrieve EPC
|
|
// properties such as confidentiality and integrity.
|
|
// SAFETY: call cpuid with valid leaves
|
|
let leaf = unsafe { std::arch::x86_64::__cpuid_count(0x12, 0x2) };
|
|
|
|
for (i, epc_section) in epc_sections.iter().enumerate() {
|
|
let subleaf_idx = i + 2;
|
|
let start = epc_section.start().raw_value();
|
|
let size = epc_section.size();
|
|
let eax = (start & 0xffff_f000) as u32 | 0x1;
|
|
let ebx = (start >> 32) as u32;
|
|
let ecx = (size & 0xffff_f000) as u32 | (leaf.ecx & 0xf);
|
|
let edx = (size >> 32) as u32;
|
|
// CPU Topology leaf 0x12
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EAX, eax);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EBX, ebx);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::ECX, ecx);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EDX, edx);
|
|
}
|
|
|
|
// Add one NULL entry to terminate the dynamic list
|
|
let subleaf_idx = epc_sections.len() + 2;
|
|
// CPU Topology leaf 0x12
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EAX, 0);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EBX, 0);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::ECX, 0);
|
|
CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EDX, 0);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod tests {
|
|
use super::*;
|
|
|
|
#[test]
|
|
fn regions_base_addr() {
|
|
let regions = arch_memory_regions();
|
|
assert_eq!(4, regions.len());
|
|
assert_eq!(GuestAddress(0), regions[0].0);
|
|
assert_eq!(GuestAddress(1 << 32), regions[1].0);
|
|
}
|
|
|
|
#[test]
|
|
fn test_system_configuration() {
|
|
let no_vcpus = 4;
|
|
let gm = GuestMemoryMmap::from_ranges(&[(GuestAddress(0), 0x10000)]).unwrap();
|
|
let config_err = configure_system(
|
|
&gm,
|
|
GuestAddress(0),
|
|
&None,
|
|
1,
|
|
Some(layout::RSDP_POINTER),
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
);
|
|
assert!(config_err.is_err());
|
|
|
|
// Now assigning some memory that falls before the 32bit memory hole.
|
|
let arch_mem_regions = arch_memory_regions();
|
|
let ram_regions: Vec<(GuestAddress, usize)> = arch_mem_regions
|
|
.iter()
|
|
.filter(|r| r.2 == RegionType::Ram && r.1 != usize::MAX)
|
|
.map(|r| (r.0, r.1))
|
|
.collect();
|
|
let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
|
|
|
|
configure_system(
|
|
&gm,
|
|
GuestAddress(0),
|
|
&None,
|
|
no_vcpus,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
)
|
|
.unwrap();
|
|
|
|
// Now assigning some memory that falls after the 32bit memory hole.
|
|
let arch_mem_regions = arch_memory_regions();
|
|
let ram_regions: Vec<(GuestAddress, usize)> = arch_mem_regions
|
|
.iter()
|
|
.filter(|r| r.2 == RegionType::Ram)
|
|
.map(|r| {
|
|
if r.1 == usize::MAX {
|
|
(r.0, 128 << 20)
|
|
} else {
|
|
(r.0, r.1)
|
|
}
|
|
})
|
|
.collect();
|
|
let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
|
|
configure_system(
|
|
&gm,
|
|
GuestAddress(0),
|
|
&None,
|
|
no_vcpus,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
)
|
|
.unwrap();
|
|
|
|
configure_system(
|
|
&gm,
|
|
GuestAddress(0),
|
|
&None,
|
|
no_vcpus,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
)
|
|
.unwrap();
|
|
}
|
|
|
|
#[test]
|
|
fn test_add_memmap_entry() {
|
|
let mut memmap: Vec<hvm_memmap_table_entry> = Vec::new();
|
|
|
|
let expected_memmap = vec![
|
|
hvm_memmap_table_entry {
|
|
addr: 0x0,
|
|
size: 0x1000,
|
|
type_: E820_RAM,
|
|
..Default::default()
|
|
},
|
|
hvm_memmap_table_entry {
|
|
addr: 0x10000,
|
|
size: 0xa000,
|
|
type_: E820_RESERVED,
|
|
..Default::default()
|
|
},
|
|
];
|
|
|
|
add_memmap_entry(&mut memmap, 0, 0x1000, E820_RAM);
|
|
add_memmap_entry(&mut memmap, 0x10000, 0xa000, E820_RESERVED);
|
|
|
|
assert_eq!(format!("{memmap:?}"), format!("{expected_memmap:?}"));
|
|
}
|
|
}
|